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Thu, 13 Oct 2022 17:57:59 +0000 Received: from offworld (ip72-199-50-187.sd.sd.cox.net [72.199.50.187]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: dave@stgolabs.net) by pdx1-sub0-mail-a274.dreamhost.com (Postfix) with ESMTPSA id 4MpHLG4kk8z4h; Thu, 13 Oct 2022 10:57:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=stgolabs.net; s=dreamhost; t=1665683879; bh=Cp5oOM4plEZlxFu/1TUngUErBCLDH5+1REIPYMGr+ls=; h=Date:From:To:Cc:Subject:Content-Type; b=gMqX1IfNm+/8OuopssrEqgr6X/AzhoG47GxacjrHLA3iFXG/zQ2RYjK8RMizeliVu mCYb7o4kNYPb0AbI3CYIowhEAOAevuPR6O++bdw5dHk/AVKUaKprYF0otM+hdledj2 5JTtimNlKW12huWB5hgrfc0CQhdaiBsKIFr8zMZs9SC+QGQtP+9V9522JerI3ujNoQ RBQw6rCPOEg2KK5x2/PpUFPONbkMO+Ve2V4DSlvFn8s5+vugvwM/lxjA7cG6tWiufM Xw9AnJwcqHxFp2iXa0eLTRUNIPmFFqBy8BYMJ19r5M2LVu1T103jDMj9DcJEFCK/Ix WDbp5WLdfbwBQ== Date: Thu, 13 Oct 2022 10:37:03 -0700 From: Davidlohr Bueso To: Jonathan Cameron Cc: dan.j.williams@intel.com, ira.weiny@intel.com, alison.schofield@intel.com, vishal.l.verma@intel.com, bwidawsk@kernel.org, a.manzanares@samsung.com, linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org Subject: Re: [PATCH] cxl: Add generic MSI/MSI-X interrupt support Message-ID: <20221013173703.th54drzlafvj74oo@offworld> References: <20221012180432.473373-1-dave@stgolabs.net> <20221013131913.0000038b@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: <20221013131913.0000038b@huawei.com> User-Agent: NeoMutt/20220429 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Thanks for having a look. On Thu, 13 Oct 2022, Jonathan Cameron wrote: >> +struct cxl_irq_cap { >> + const char *name; >> + int (*get_max_msgnum)(struct cxl_dev_state *cxlds); > >For the CPMU case I need to walk the register locator dvsec block so need >the callback to take the pci_dev not the cxl_dev_state. Hmm ok, however maybe I'm missing something, but given a pdev, do we have a way to get back to the cxlds? ... >> static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) >> { >> struct cxl_register_map map; >> @@ -498,6 +558,9 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) >> if (IS_ERR(cxlmd)) >> return PTR_ERR(cxlmd); >> >> + /* TODO: When there are users, this return value must be checked */ >> + cxl_pci_alloc_irq_vectors(cxlds); >> + > >Gut feeling is this will end up moving ahead of any of the sub device creation >because many of them end up needing interrupts. > >Also check response from the start - can't see a reason to not do so as we >won't be registering any at all if no callbacks provided. > >So I'd move it above the devm_cxl_add_memdev() call. Will do. In addition, are you ok with grouping the irq setup for each cxl feature/component, ie: if (cxl_pci_alloc_irq_vectors(cxlds) > 0) { cxl_setup_mbox_irq(); cxl_setup_events_irq(); cxl_setup_pmu_irq(); } I ask mostly from the mailbox perspective, in that we already have a mbox setup call and can certainly understand if people would prefer it there, but I tend to prefer the above (logically wrt irqs). Thanks, Davidlohr