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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id x3-20020a4ae783000000b004807de5c302sm107810oov.17.2022.10.13.12.12.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Oct 2022 12:12:49 -0700 (PDT) Received: (nullmailer pid 92150 invoked by uid 1000); Thu, 13 Oct 2022 19:12:49 -0000 Date: Thu, 13 Oct 2022 14:12:49 -0500 From: Rob Herring To: Dominic Rath Cc: krzysztof.kozlowski+dt@linaro.org, tjoseph@cadence.com, bhelgaas@google.com, lpieralisi@kernel.org, nm@ti.com, vigneshr@ti.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Alexander Bahle , Dominic Rath Subject: Re: [PATCH 1/3] dt-bindings: PCI: cdns: Add PHY latency properties Message-ID: <20221013191249.GA38183-robh@kernel.org> References: <20221013062649.303184-1-dominic.rath@ibv-augsburg.de> <20221013062649.303184-2-dominic.rath@ibv-augsburg.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221013062649.303184-2-dominic.rath@ibv-augsburg.de> X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00, FREEMAIL_ENVFROM_END_DIGIT,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Oct 13, 2022 at 08:26:47AM +0200, Dominic Rath wrote: > From: Alexander Bahle > > Add "cdns,tx-phy-latency-ps" and "cdns,rx-phy-latency-ps" DT bindings for > setting the PCIe PHY latencies. > The properties expect a list of uint32 PHY latencies in picoseconds for > every supported speed starting at PCIe Gen1, e.g.: > > max-link-speed = <2>; > tx-phy-latency-ps = <100000 200000>; /* Gen1: 100ns, Gen2: 200ns */ > rx-phy-latency-ps = <150000 250000>; /* Gen1: 150ns, Gen2: 250ns */ These are a property of the PHY or PCI host? Sounds like PHY to me and that should be in the PHY node. No reason the PCI driver can't go read PHY node properties. If PTM is a standard PCIe thing, then I don't think these should be Cadence specific. IOW, drop 'cdns'. Rob