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To:     "Gupta, Nipun" <Nipun.Gupta@amd.com>,
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CC:     "okaya@kernel.org" <okaya@kernel.org>,
        "Anand, Harpreet" <harpreet.anand@amd.com>,
        "Agarwal, Nikhil" <nikhil.agarwal@amd.com>,
        "Simek, Michal" <michal.simek@amd.com>,
        "Radovanovic, Aleksandar" <aleksandar.radovanovic@amd.com>,
        "git (AMD-Xilinx)" <git@amd.com>
Subject: RE: [RFC PATCH v4 3/8] iommu/arm-smmu-v3: support ops registration
 for CDX bus
Thread-Topic: [RFC PATCH v4 3/8] iommu/arm-smmu-v3: support ops registration
 for CDX bus
Thread-Index: AQHY34dTQC9mGlmp3UOx5Opq013mC64NUdeg
Date:   Fri, 14 Oct 2022 04:51:51 +0000
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[AMD Official Use Only - General]

This patch will be rebased on top of https://lore.kernel.org/linux-iommu/co=
ver.1660572783.git.robin.murphy@arm.com/T/#t
in next respin.

Regards,
Nipun

> -----Original Message-----
> From: Nipun Gupta <nipun.gupta@amd.com>
> Sent: Friday, October 14, 2022 10:11 AM
> To: robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org;
> gregkh@linuxfoundation.org; rafael@kernel.org; eric.auger@redhat.com;
> alex.williamson@redhat.com; cohuck@redhat.com; Gupta, Puneet (DCG-ENG)
> <puneet.gupta@amd.com>; song.bao.hua@hisilicon.com;
> mchehab+huawei@kernel.org; maz@kernel.org; f.fainelli@gmail.com;
> jeffrey.l.hugo@gmail.com; saravanak@google.com; Michael.Srba@seznam.cz;
> mani@kernel.org; yishaih@nvidia.com; jgg@ziepe.ca; jgg@nvidia.com;
> robin.murphy@arm.com; will@kernel.org; joro@8bytes.org;
> masahiroy@kernel.org; ndesaulniers@google.com; linux-arm-
> kernel@lists.infradead.org; linux-kbuild@vger.kernel.org; linux-
> kernel@vger.kernel.org; devicetree@vger.kernel.org; kvm@vger.kernel.org
> Cc: okaya@kernel.org; Anand, Harpreet <harpreet.anand@amd.com>; Agarwal,
> Nikhil <nikhil.agarwal@amd.com>; Simek, Michal <michal.simek@amd.com>;
> Radovanovic, Aleksandar <aleksandar.radovanovic@amd.com>; git (AMD-Xilinx=
)
> <git@amd.com>; Gupta, Nipun <Nipun.Gupta@amd.com>
> Subject: [RFC PATCH v4 3/8] iommu/arm-smmu-v3: support ops registration f=
or
> CDX bus
>=20
> With new CDX bus supported for AMD FPGA devices on ARM
> platform, the bus requires registration for the SMMU v3
> driver.
>=20
> Signed-off-by: Nipun Gupta <nipun.gupta@amd.com>
> ---
>  drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 16 ++++++++++++++--
>  1 file changed, 14 insertions(+), 2 deletions(-)
>=20
> diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> index d32b02336411..8ec9f2baf12d 100644
> --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
> @@ -29,6 +29,7 @@
>  #include <linux/platform_device.h>
>=20
>  #include <linux/amba/bus.h>
> +#include <linux/cdx/cdx_bus.h>
>=20
>  #include "arm-smmu-v3.h"
>  #include "../../iommu-sva-lib.h"
> @@ -3690,16 +3691,27 @@ static int arm_smmu_set_bus_ops(struct
> iommu_ops *ops)
>  		if (err)
>  			goto err_reset_pci_ops;
>  	}
> +#endif
> +#ifdef CONFIG_CDX_BUS
> +	if (cdx_bus_type.iommu_ops !=3D ops) {
> +		err =3D bus_set_iommu(&cdx_bus_type, ops);
> +		if (err)
> +			goto err_reset_amba_ops;
> +	}
>  #endif
>  	if (platform_bus_type.iommu_ops !=3D ops) {
>  		err =3D bus_set_iommu(&platform_bus_type, ops);
>  		if (err)
> -			goto err_reset_amba_ops;
> +			goto err_reset_cdx_ops;
>  	}
>=20
>  	return 0;
>=20
> -err_reset_amba_ops:
> +err_reset_cdx_ops:
> +#ifdef CONFIG_CDX_BUS
> +	bus_set_iommu(&cdx_bus_type, NULL);
> +#endif
> +err_reset_amba_ops: __maybe_unused;
>  #ifdef CONFIG_ARM_AMBA
>  	bus_set_iommu(&amba_bustype, NULL);
>  #endif
> --
> 2.25.1