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[2620:137:e000::1:20]) by mx.google.com with ESMTP id 26-20020a170906309a00b007707eb353eesi2734351ejv.305.2022.10.14.17.25.04; Fri, 14 Oct 2022 17:25:29 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcdkim header.b=ZTJwN2Ir; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229573AbiJNXxl (ORCPT + 99 others); Fri, 14 Oct 2022 19:53:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46580 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229436AbiJNXxk (ORCPT ); Fri, 14 Oct 2022 19:53:40 -0400 Received: from alexa-out-sd-02.qualcomm.com (alexa-out-sd-02.qualcomm.com [199.106.114.39]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC4786374; Fri, 14 Oct 2022 16:53:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1665791618; x=1697327618; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=rbflSGtIpPJO6C65/fJEG2ZGnDtsLTlgBQPQCuKjCoM=; b=ZTJwN2IrGuyL287wDDpMJC7ncJW5uA3g1AKIC3uZTtmVt8wIoqHpHeMF lpOErIvq1ghpbpyjmMrCUWaYwWmYQ8kqVL4TBvCTyhlPRSHT+tCj4/Vid TjoDwZFi531MIfhRoEpNvt0VZIzWbxFO3CIJrb07yaI6NwuZp/Eex0G/N s=; Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-02.qualcomm.com with ESMTP; 14 Oct 2022 16:53:38 -0700 X-QCInternal: smtphost Received: from nasanex01b.na.qualcomm.com ([10.46.141.250]) by ironmsg04-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2022 16:53:37 -0700 Received: from [10.110.77.177] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 14 Oct 2022 16:53:37 -0700 Message-ID: Date: Fri, 14 Oct 2022 16:53:36 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.2.2 Subject: Re: [PATCH v2 0/6] clk: qcom: Add clocks for the QDU1000 and QRU1000 SoCs To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Thomas Gleixner , Marc Zyngier CC: , , , References: <20221014221011.7360-1-quic_molvera@quicinc.com> Content-Language: en-US From: Melody Olvera In-Reply-To: <20221014221011.7360-1-quic_molvera@quicinc.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/14/2022 3:10 PM, Melody Olvera wrote: > This series adds the GCC, RPMh, and PDC clock support required for the > QDU1000 and QRU1000 SoCs along with the devicetree bindings for them. > > The Qualcomm Technologies, Inc. Distributed Unit 1000 and Radio Unit > 1000 are new SoCs meant for enabling Open RAN solutions. See more at > https://www.qualcomm.com/content/dam/qcomm-martech/dm-assets/documents/qualcomm_5g_ran_platforms_product_brief.pdf > > This patchset is based on the YAML conversion patch [1] submitted already. > > [1] https://lore.kernel.org/r/20220103074348.6039-1-luca.weiss@fairphone.com Changes from V1: - fixed alphabetic sorting - moved clk-branch changes to a separate commit - revised bindings > Imran Shaik (1): > clk: qcom: branch: Add BRANCH_HALT_INVERT flag support for branch > clocks > > Melody Olvera (4): > dt-bindings: clock: Add QDU1000 and QRU1000 GCC clock bindings > dt-bindings: clock: Add RPMHCC bindings for QDU1000 and QRU1000 > clk: qcom: Add support for QDU1000 and QRU1000 RPMh clocks > dt-bindings: qcom,pdc: Introduce pdc bindings for QDU1000 and QRU1000 > > Taniya Das (1): > clk: qcom: Add QDU1000 and QRU1000 GCC support > > .../bindings/clock/qcom,gcc-qdu1000.yaml | 70 + > .../bindings/clock/qcom,rpmhcc.yaml | 2 + > .../interrupt-controller/qcom,pdc.yaml | 2 + > drivers/clk/qcom/Kconfig | 8 + > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/clk-branch.c | 5 + > drivers/clk/qcom/clk-branch.h | 2 + > drivers/clk/qcom/clk-rpmh.c | 14 + > drivers/clk/qcom/gcc-qdu1000.c | 2644 +++++++++++++++++ > include/dt-bindings/clock/qcom,gcc-qdu1000.h | 170 ++ > 10 files changed, 2918 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-qdu1000.yaml > create mode 100644 drivers/clk/qcom/gcc-qdu1000.c > create mode 100644 include/dt-bindings/clock/qcom,gcc-qdu1000.h > > > base-commit: dca0a0385a4963145593ba417e1417af88a7c18d