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Mon, 17 Oct 2022 05:52:01 +0000 Received: from DU0PR04MB9417.eurprd04.prod.outlook.com ([fe80::a5ff:3d28:4bbc:e1ed]) by DU0PR04MB9417.eurprd04.prod.outlook.com ([fe80::a5ff:3d28:4bbc:e1ed%6]) with mapi id 15.20.5723.032; Mon, 17 Oct 2022 05:52:01 +0000 From: Peng Fan To: Rob Herring , "Peng Fan (OSS)" CC: "gregkh@linuxfoundation.org" , "krzysztof.kozlowski+dt@linaro.org" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , Xu Yang , "kernel@pengutronix.de" , "festevam@gmail.com" , dl-linux-imx , "linux-usb@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Jun Li Subject: RE: [PATCH V2 4/6] dt-bindings: usb: ci-hdrc-usb2: convert to DT schema format Thread-Topic: [PATCH V2 4/6] dt-bindings: usb: ci-hdrc-usb2: convert to DT schema format Thread-Index: AQHY37JprV1rugCYiEuEviVPf0orFa4N8xMAgAQchuA= Date: Mon, 17 Oct 2022 05:52:01 +0000 Message-ID: References: <20221014095148.2063669-1-peng.fan@oss.nxp.com> <20221014095148.2063669-5-peng.fan@oss.nxp.com> <20221014142832.GA1903421-robh@kernel.org> In-Reply-To: <20221014142832.GA1903421-robh@kernel.org> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DU0PR04MB9417.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: d6c88601-2330-4022-967e-08dab003b5fa X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Oct 2022 05:52:01.0679 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: W3a/aCl1aKrA1b2BdA4FXd4GGDGqAr7kOlQcqOez5W3pNmHnWQQqRgVlnDdTWjaC22ashSMjHP24Gc3pYNTG+A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB7139 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Rob, > Subject: Re: [PATCH V2 4/6] dt-bindings: usb: ci-hdrc-usb2: convert to DT > schema format >=20 > On Fri, Oct 14, 2022 at 05:51:46PM +0800, Peng Fan (OSS) wrote: > > From: Peng Fan > > > > Convert the binding to DT schema format > > > > Signed-off-by: Peng Fan > > --- > > .../devicetree/bindings/usb/ci-hdrc-usb2.txt | 158 -------- > > .../devicetree/bindings/usb/ci-hdrc-usb2.yaml | 341 ++++++++++++++++++ > > 2 files changed, 341 insertions(+), 158 deletions(-) delete mode > > 100644 Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt > > create mode 100644 > > Documentation/devicetree/bindings/usb/ci-hdrc-usb2.yaml >=20 > > diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.yaml > > b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.yaml > > new file mode 100644 > > index 000000000000..ed03649f17a6 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.yaml > > @@ -0,0 +1,341 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 > > +--- > > +$id: > > > +https://eur01.safelinks.protection.outlook.com/?url=3Dhttp%3A%2F%2Fdevi > > +cetree.org%2Fschemas%2Fusb%2Fci-hdrc- > usb2.yaml%23&data=3D05%7C01%7C > > > +peng.fan%40nxp.com%7Cc82aff1e7786408bdfb908daadf05fba%7C686ea1 > d3bc2b4 > > > +c6fa92cd99c5c301635%7C0%7C0%7C638013545157576176%7CUnknown% > 7CTWFpbGZs > > > +b3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6 > Mn0%3 > > > +D%7C3000%7C%7C%7C&sdata=3DWCoRU5%2FlPpdKF984bqAmU7WPU8 > XbDvBZoVyJ6K3 > > +nggY%3D&reserved=3D0 > > +$schema: > > > +https://eur01.safelinks.protection.outlook.com/?url=3Dhttp%3A%2F%2Fdevi > > +cetree.org%2Fmeta- > schemas%2Fcore.yaml%23&data=3D05%7C01%7Cpeng.fan% > > > +40nxp.com%7Cc82aff1e7786408bdfb908daadf05fba%7C686ea1d3bc2b4c6 > fa92cd9 > > > +9c5c301635%7C0%7C0%7C638013545157576176%7CUnknown%7CTWFpb > GZsb3d8eyJWI > > > +joiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7 > C3000% > > > +7C%7C%7C&sdata=3Dl6g5TrxpwRjZqUgRmqpAbhCIO4%2BLRp0y1IFV5SS > nkx0%3D&a > > +mp;reserved=3D0 > > + > > +title: USB2 ChipIdea USB controller for ci13xxx Binding > > + > > +maintainers: > > + - Xu Yang > > + > > +properties: > > + compatible: > > + oneOf: > > + - enum: > > + - chipidea,usb2 > > + - lsi,zevio-usb > > + - nvidia,tegra20-udc > > + - nvidia,tegra30-udc > > + - nvidia,tegra114-udc > > + - nvidia,tegra124-udc > > + - qcom,ci-hdrc > > + - items: > > + - enum: > > + - fsl,imx23-usb > > + - fsl,imx25-usb > > + - fsl,imx28-usb > > + - fsl,imx6q-usb > > + - fsl,imx6sl-usb > > + - fsl,imx6sx-usb > > + - fsl,imx6ul-usb > > + - fsl,imx7d-usb > > + - const: fsl,imx27-usb > > + - items: > > + - const: fsl,imx7ulp-usb > > + - const: fsl,imx6ul-usb > > + - items: > > + - const: xlnx,zynq-usb-2.20a > > + - const: chipidea,usb2 > > + > > + "#address-cells": > > + const: 1 > > + > > + "#size-cells": > > + const: 0 > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + maxItems: 1 > > + > > + clocks: > > + minItems: 1 > > + maxItems: 2 > > + > > + dr_mode: true > > + > > + phy_type: true > > + > > + itc-setting: > > + description: > > + interrupt threshold control register control, the setting should= be > > + aligned with ITC bits at register USBCMD. > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + > > + ahb-burst-config: > > + description: > > + it is vendor dependent, the required value should be aligned wit= h > > + AHBBRST at SBUSCFG, the range is from 0x0 to 0x7. This property = is > > + used to change AHB burst configuration, check the chipidea spec = for > > + meaning of each value. If this property is not existed, it will = use > > + the reset value. > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + minimum: 0x0 > > + maximum: 0x7 > > + > > + tx-burst-size-dword: > > + description: > > + it is vendor dependent, the tx burst size in dword (4 bytes), Th= is > > + register represents the maximum length of a the burst in 32-bit > > + words while moving data from system memory to the USB bus, the > value > > + of this property will only take effect if property "ahb-burst-co= nfig" > > + is set to 0, if this property is missing the reset default of th= e > > + hardware implementation will be used. > > + $ref: /schemas/types.yaml#/definitions/uint32 >=20 > Constraints? I assume 2^32 is not valid... Actually I am not sure, per txt binding, it is vendor dependent. i.MX has value 0x8 or 0x10, but I am not other vendors. >=20 > > + > > + rx-burst-size-dword: > > + description: > > + it is vendor dependent, the rx burst size in dword (4 bytes), Th= is > > + register represents the maximum length of a the burst in 32-bit = words > > + while moving data from the USB bus to system memory, the value o= f > > + this property will only take effect if property "ahb-burst-confi= g" > > + is set to 0, if this property is missing the reset default of th= e > > + hardware implementation will be used. > > + $ref: /schemas/types.yaml#/definitions/uint32 >=20 > Constraints? Vendor dependent, I am not sure. >=20 > > + > > + extcon: > > + description: | > > + Phandles to external connector devices. First phandle should poi= nt > > + to external connector, which provide "USB" cable events, the sec= ond > > + should point to external connector device, which provide "USB-HO= ST" > > + cable events. If one of the external connector devices is not > > + required, empty <0> phandle should be specified. > > + > > + phy-clkgate-delay-us: > > + description: | > > + The delay time (us) between putting the PHY into low power mode > and > > + gating the PHY clock. > > + > > + non-zero-ttctrl-ttha: > > + description: | > > + After setting this property, the value of register ttctrl.ttha > > + will be 0x7f; if not, the value will be 0x0, this is the default > > + value. It needs to be very carefully for setting this property, = it > > + is recommended that consult with your IC engineer before setting > > + this value. On the most of chipidea platforms, the "usage_tt" f= lag > > + at RTL is 0, so this property only affects siTD. > > + > > + If this property is not set, the max packet size is 1023 bytes, = and > > + if the total of packet size for pervious transactions are more t= han > > + 256 bytes, it can't accept any transactions within this frame. T= he > > + use case is single transaction, but higher frame rate. > > + > > + If this property is set, the max packet size is 188 bytes, it ca= n > > + handle more transactions than above case, it can accept transact= ions > > + until it considers the left room size within frame is less than = 188 > > + bytes, software needs to make sure it does not send more than 90= % > > + maximum_periodic_data_per_frame. The use case is multiple > > + transactions, but less frame rate. > > + > > + mux-controls: > > + description: | > > + The mux control for toggling host/device output of this controll= er. > > + It's expected that a mux state of 0 indicates device mode and a = mux > > + state of 1 indicates host mode. >=20 > maxItems: 1 Fix in v3. >=20 > > + > > + mux-control-names: > > + const: usb_switch > > + > > + pinctrl-names: > > + description: | > > + Names for optional pin modes in "default", "host", "device". > > + In case of HSIC-mode, "idle" and "active" pin modes are mandator= y. > > + In this case, the "idle" state needs to pull down the data and > > + strobe pin and the "active" state needs to pull up the strobe pi= n. >=20 > The names need to be constraints, not freeform text. I am not sure, I have added constraints in allOf section. >=20 > > + > > + pinctrl-0: > > + maxItems: 1 > > + > > + pinctrl-1: > > + maxItems: 1 > > + > > + phys: > > + maxItems: 1 > > + > > + phy-names: > > + const: usb-phy > > + > > + vbus-supply: > > + description: reference to the VBUS regulator. > > + > > + fsl,usbmisc: > > + description: > > + Phandler of non-core register device, with one argument that > > + indicate usb controller index > > + $ref: /schemas/types.yaml#/definitions/phandle-array >=20 > items: > - items: > - description: phandle to usbmisc node > - description: index of usb controller >=20 > > + > > + disable-over-current: > > + description: disable over current detect >=20 > type? It is a Boolean type. I should add "type: boolean" >=20 > > + > > + over-current-active-low: > > + description: over current signal polarity is active low >=20 > type? type: boolean >=20 > > + > > + over-current-active-high: > > + description: | > > + Over current signal polarity is active high. It's recommended to > > + specify the over current polarity. >=20 > type? type: boolean >=20 > > + > > + power-active-high: > > + description: power signal polarity is active high >=20 > type? type: boolean >=20 > > + > > + external-vbus-divider: > > + description: enables off-chip resistor divider for Vbus >=20 > type? type: boolean >=20 > > + > > + samsung,picophy-pre-emp-curr-control: > > + description: | > > + HS Transmitter Pre-Emphasis Current Control. This signal control= s > > + the amount of current sourced to the USB_OTG*_DP and > USB_OTG*_DN > > + pins after a J-to-K or K-to-J transition. The range is from 0x0 = to > > + 0x3, the default value is 0x1. Details can refer to > TXPREEMPAMPTUNE0 > > + bits of USBNC_n_PHY_CFG1. > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + minimum: 0x0 > > + maximum: 0x3 > > + > > + samsung,picophy-dc-vol-level-adjust: > > + description: | > > + HS DC Voltage Level Adjustment. Adjust the high-speed transmitte= r > DC > > + level voltage. The range is from 0x0 to 0xf, the default value i= s > > + 0x3. Details can refer to TXVREFTUNE0 bits of USBNC_n_PHY_CFG1. > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + minimum: 0x0 > > + maximum: 0xf > > + > > + usb-phy: > > + description: phandle for the PHY device. Use "phys" instead. > > + $ref: /schemas/types.yaml#/definitions/phandle > > + deprecated: true > > + > > + fsl,usbphy: > > + description: phandle of usb phy that connects to the port. Use "ph= ys" > instead. > > + $ref: /schemas/types.yaml#/definitions/phandle > > + deprecated: true > > + > > +patternProperties: > > + "ethernet@[0-9a-f]$": >=20 > This is board specific and shouldn't be part of the schema. But you do ne= ed > to define child nodes with a reference to common usb schemas. The txt binding has the child node usbnet: ethernet@1 { compatible =3D "usb424,9730"; reg =3D <1>; }; I am not sure how to support it. If I not add such patterProperties, there = will be dt binding check error. The child node is a usb ethernet, I think common usb schemas not has that. If you have a simple example, I could follow that.=20 >=20 > > + description: The hard wired USB devices > > + type: object > > + $ref: /schemas/net/microchip,lan95xx.yaml > > + > > +required: > > + - compatible > > + - reg > > + - interrupts > > + > > +allOf: > > + - $ref: usb-hcd.yaml# > > + - $ref: usb-drd.yaml# > > + - if: > > + properties: > > + mux-controls: > > + true > > + then: > > + properties: > > + mux-control-names: > > + const: usb_switch > > + - if: > > + properties: > > + phy_type: > > + const: hsic > > + > > + required: > > + - phy_type > > + then: > > + properties: > > + pinctrl-names: > > + items: > > + - const: idle > > + - const: active > > + else: > > + properties: > > + pinctrl-names: > > + oneOf: > > + - items: > > + - const: default > > + - enum: > > + - host > > + - device > > + - items: > > + - const: default >=20 > 'minItems: 1' in the 1st (oneOf) entry and drop the 2nd entry. ok >=20 > > + - if: > > + properties: > > + compatible: > > + contains: > > + enum: > > + - chipidea,usb2 > > + - lsi,zevio-usb > > + - nvidia,tegra20-udc > > + - nvidia,tegra30-udc > > + - nvidia,tegra114-udc > > + - nvidia,tegra124-udc > > + - qcom,ci-hdrc > > + - xlnx,zynq-usb-2.20a > > + then: > > + properties: > > + fsl,usbmisc: false > > + disable-over-current: false > > + over-current-active-low: false > > + over-current-active-high: false > > + power-active-high: false > > + external-vbus-divider: false > > + samsung,picophy-pre-emp-curr-control: false > > + samsung,picophy-dc-vol-level-adjust: false > > + > > +additionalProperties: false >=20 > unevaluatedProperties: false Will add this. Thanks, Peng. >=20 > > + > > +examples: > > + - | > > + #include > > + #include > > + > > + usb@f7ed0000 { > > + compatible =3D "chipidea,usb2"; > > + reg =3D <0xf7ed0000 0x10000>; > > + interrupts =3D ; > > + clocks =3D <&chip CLKID_USB0>; > > + phys =3D <&usb_phy0>; > > + phy-names =3D "usb-phy"; > > + vbus-supply =3D <®_usb0_vbus>; > > + itc-setting =3D <0x4>; /* 4 micro-frames */ > > + /* Incremental burst of unspecified length */ > > + ahb-burst-config =3D <0x0>; > > + tx-burst-size-dword =3D <0x10>; /* 64 bytes */ > > + rx-burst-size-dword =3D <0x10>; > > + extcon =3D <0>, <&usb_id>; > > + phy-clkgate-delay-us =3D <400>; > > + mux-controls =3D <&usb_switch>; > > + mux-control-names =3D "usb_switch"; > > + }; > > + > > + # Example for HSIC: > > + - | > > + #include > > + #include > > + > > + usb@2184400 { > > + compatible =3D "fsl,imx6q-usb", "fsl,imx27-usb"; > > + reg =3D <0x02184400 0x200>; > > + interrupts =3D <0 41 IRQ_TYPE_LEVEL_HIGH>; > > + clocks =3D <&clks IMX6QDL_CLK_USBOH3>; > > + fsl,usbphy =3D <&usbphynop1>; > > + fsl,usbmisc =3D <&usbmisc 2>; > > + phy_type =3D "hsic"; > > + dr_mode =3D "host"; > > + ahb-burst-config =3D <0x0>; > > + tx-burst-size-dword =3D <0x10>; > > + rx-burst-size-dword =3D <0x10>; > > + pinctrl-names =3D "idle", "active"; > > + pinctrl-0 =3D <&pinctrl_usbh2_idle>; > > + pinctrl-1 =3D <&pinctrl_usbh2_active>; > > + #address-cells =3D <1>; > > + #size-cells =3D <0>; > > + > > + usbnet: ethernet@1 { > > + compatible =3D "usb424,9730"; > > + reg =3D <1>; > > + }; > > + }; > > + > > +... > > -- > > 2.37.1 > > > >