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Received: from CO6PR12MB5444.namprd12.prod.outlook.com (2603:10b6:5:35e::8) by MW4PR12MB7167.namprd12.prod.outlook.com (2603:10b6:303:225::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5723.20; Mon, 17 Oct 2022 08:41:01 +0000 Received: from CO6PR12MB5444.namprd12.prod.outlook.com ([fe80::c0e5:f111:3e59:7c66]) by CO6PR12MB5444.namprd12.prod.outlook.com ([fe80::c0e5:f111:3e59:7c66%5]) with mapi id 15.20.5723.033; Mon, 17 Oct 2022 08:41:01 +0000 Message-ID: <0571554f-ee19-39ba-c0ce-bab544ebfde2@nvidia.com> Date: Mon, 17 Oct 2022 09:40:53 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.2.2 Subject: Re: [PATCH] PCI: tegra: Use PCI_CONF1_EXT_ADDRESS() macro Content-Language: en-US To: Lorenzo Pieralisi Cc: =?UTF-8?Q?Pali_Roh=c3=a1r?= , Thierry Reding , Rob Herring , =?UTF-8?Q?Krzysztof_Wilczy=c5=84ski?= , Bjorn Helgaas , Vidya Sagar , linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org References: <20220928121911.14994-1-pali@kernel.org> <220b0fe7-8b7b-cf9b-e28d-d9d81647fb80@nvidia.com> <20221011161638.ycxpg3ox2wv63vym@pali> <18a48407-9fd7-175d-0c7f-5702b077f13d@nvidia.com> From: Jon Hunter In-Reply-To: Content-Type: text/plain; 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PCIe config read and write operations >>> needs to be 4-byte aligned, so normally it is done by calculating 4-byte >>> aligned base address and then using appropriate cpu load/store >>> instruction to access just defined size/offset of 4-byte config space >>> register. >>> >>> pci-tegra.c is using common helper functions pci_generic_config_read() >>> and pci_generic_config_write(), which expects final address with offset, >>> and not 4-byte aligned address. >>> >>> I'm not sure what should be the proper fix, but for me it looks like >>> that pci_generic_config_read() and pci_generic_config_write() could be >>> adjusted to handle it. >>> >>> In any case, above patch is a regressions and I see there two options >>> for now: >>> >>> 1) Reverting that patch >>> >>> 2) Adding "offset |= where & 0x3;" after the PCI_CONF1_EXT_ADDRESS() >>> macro to set also lower 2 bits of accessed register. >>> >>> Jon, Lorenzo, what do you think? Could you test if 2) is working fine? >> >> >> I tested 'offset |= where & 0xff' which is essentially the same as the above >> and that is working and so I am sure that the above works too. However, I do >> wonder if reverting is simpler because we already have a '& >> ~PCI_CONF1_ENABLE' and now adding '| where & 0x3' seems to diminish the >> value of this change. > > Hi Jon, > > it is unfortunate but I think we should proceed with a revert, please > send it and I shall ask Bjorn to send it for one of the upcoming -rcX. I have sent a revert for this change. Thanks Jon -- nvpublic