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Date:   Mon, 17 Oct 2022 10:31:53 +0100
From:   Paul Cercueil <paul@crapouillou.net>
Subject: Re: [PATCH 7/8] serial: 8250/ingenic: Add support for the
 JZ4750/JZ4755 SoCs
To:     Siarhei Volkau <lis8215@gmail.com>
Cc:     Arnd Bergmann <arnd@arndb.de>, kernel test robot <lkp@intel.com>,
        kbuild-all@lists.01.org,
        Michael Turquette <mturquette@baylibre.com>,
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        Rob Herring <robh+dt@kernel.org>,
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        Vinod Koul <vkoul@kernel.org>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
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Hi Siarhei,

Le dim., oct. 16 2022 at 21:39:48 +0300, Siarhei Volkau=20
<lis8215@gmail.com> a =C3=A9crit :
> =D1=87=D1=82, 13 =D0=BE=D0=BA=D1=82. 2022 =D0=B3. =D0=B2 21:56, Siarhei V=
olkau=20
> <lis8215@gmail.com>:
>=20
>>  > Just disable the divider in ingenic_fixup_fdt() in
>=20
>>  I'll check that.
>=20
> I checked that approach: serial seems to be working as expected,
> but not all the time: there's a time period when the CGU driver
> started but serial console driver is still early one.
> In my case UART produces garbage at that period since CGU
> needs to enable clock divider back: ext is 24MHz but 12MHz
> required for audio codec and USB to function properly.

What I'd do, is just force-enable it to 12 MHz in ingenic_fixup_fdt(),=20
since the programming manual basically says that 24 MHz does not work=20
properly.

Then in the earlycon setup code hardcode the /2 divider with a big fat=20
comment about why it's there.

Cheers,
-Paul

> So I think Arnd's approach:
>=20
>>  the hardware should already be in a working state,
>>  with no need to touch it during early boot.
>=20
> shall resolve the problem, although I can't check it on all supported
> hardware.
>=20
> BR,
> Siarhei