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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?cakVetwUX/3aJsJGL8xMJs0GzokEpaozvOGLkeBFfMQiVdRfncLp+gB01UoM?= =?us-ascii?Q?4TGc5fHeDvKo6rOW5Fgi7xQnSFZrf+WbLPDFdFK+jcDmZ/YhoS3kJvgF1CAv?= =?us-ascii?Q?HKzyQKZJRkmAnmMYcw5SuqzFt3BezwJa+zlKJ49D2rg3YWQFHP7dMBkx+h3T?= =?us-ascii?Q?3ziG8ir7BAwsOcxIJJUb6mJKyBSFroobmQd9VUxoLbQGvWAuJ2dy1TK1Y2Pn?= =?us-ascii?Q?9YCsA/lMDMFxMwFB2UKFg9BP1MMUVTolDgLsrP8/LlXEe+jHx8l3hZEKZ9DU?= =?us-ascii?Q?2ySg/I/3fC35PWPvnkspyfMniqNXKQwKSoGNjobsOo5f/iMoEvMop/mmuw8U?= =?us-ascii?Q?HOihgEl8MyFrtXhyPtqpX6LoiUsteOiQZzmA0qVUAa9i79aOWiloTK4t4uej?= =?us-ascii?Q?cA4orGZ3JWr26MpZCkYNMgLYxn1Lr1BvH4C0IV+YXl3ciCYEN4mfyXEJxmM+?= =?us-ascii?Q?qa7xpFpj03N/NwSuHanj3mNQZuQYDM1hDWCRmCcu7eJ0vLF2S7UQl9agDmHQ?= =?us-ascii?Q?5MRPmuTTPlK8aTmlOaci/vj1802sIKSAiqveuTGRpavVrIv/HKg1C6Ok+jl2?= =?us-ascii?Q?pE4qfQNMm/+u7URmtGnK8qRc+AcEgl+4J7LYFAY3uZIa2gnQtnmXKgC97OwT?= =?us-ascii?Q?SWC43A8+ZV4LSJIBJgKYQmPMORliGvejPaZyfAvX8/FK3t5b7uRKbWY7HMv3?= =?us-ascii?Q?7w5CgoMwoq7XAkC+hiWw2IhKhV57VKkXip85kNyixpP1vluPVo56DPCrAjRV?= =?us-ascii?Q?ZnzSrV1BgJhba8bGjqvALqQoxKFCJIQiGg3W5BPfxBS8bA7qctMpsa96EvH8?= =?us-ascii?Q?g47/il+uHTVQ2hL71ERIOQJUzC1KaNg5TXTM/I3n/Pkf+63j1+KcdG39unD7?= =?us-ascii?Q?Et2krTQcuhBMcGkK1sxbkkmSzfaVhWKt/YSh1mRoHd0SAuYWpJnf/EC1QMfY?= =?us-ascii?Q?vBe5wiw4P/d6X5ujQccfYux7XEh29R1va5y4eh9uRgrSzfu3ZPX5RW1jljee?= =?us-ascii?Q?obhU96p+skCRIbAqbDCo3k+gGIj3Rw6TKIDC4IZFxticeukD3d5qX5aZMV5+?= =?us-ascii?Q?o8sEBEcPbhEm7Dcoaqa0DcKPymCiClStc4vtqyZf97V65nD8SWDIavizdSnb?= =?us-ascii?Q?iXhGqnJUKr0beOw17Xq7WrB/bq9R5JM4G1wJEWUvRt0gn6LW1baEPma3Xfoy?= =?us-ascii?Q?7G5+MsnJ3X4zB/7HYdI1taqYhr7aJDuZar3fAdhSrxnkKiWbrvszdwmwXzmR?= =?us-ascii?Q?SFGm0AydxuHpOV/IUXEmrAC1Nkk2R91xNyLfA/ePEcyNXaJlYi9BRuf64ewe?= =?us-ascii?Q?cJ9WxxXR1P6++KehCIxrBFes+5LY1RP/qaNkWGiwSaSm6niu22M0E46TkQcb?= =?us-ascii?Q?n7CckQFqbN3g7TdyAVlTR/fRItUnhGWW7zBRGEfU4SnaSMqKv/kxkazw4+fi?= =?us-ascii?Q?zOwfyWKanYlkySV/aZdeTIEECUtVwFtNKX+qo/03ywBRMYrM5imBvL45N/q6?= =?us-ascii?Q?vSLc1htlA3h4duvHDg5ug1QV8GWiyrhMGiH/ypENl/Aezx7BoSVz/DZYIJxM?= =?us-ascii?Q?FQU61DF+dJPpDyklTrnXSS/tCsxMO3p38OUNP72C?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 07f59069-2489-4720-03ed-08dab02e0f0b X-MS-Exchange-CrossTenant-AuthSource: DM5PR12MB2504.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Oct 2022 10:55:10.2616 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 2PIGrMLOzV+Mhq729P8vhERAtUQPgFXLUU5M70THnBh9rNbLL4k2W1q9FInW+DdwnZvIfKeRfP+vqQYLTP8rAw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5909 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Oct 11, 2022 at 12:22:45AM +0800, Yuan, Perry wrote: > Add Energy Performance Preference support for AMD SOCs which do not > contain a designated MSR for CPPC support. A shared memory interface > is used for CPPC on these SOCs and the ACPI PCC channel is used to > enable EPP and reset the desired performance. > > Signed-off-by: Perry Yuan > --- > drivers/cpufreq/amd-pstate.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c > index 2d28f458589c..08f9e335f97c 100644 > --- a/drivers/cpufreq/amd-pstate.c > +++ b/drivers/cpufreq/amd-pstate.c > @@ -135,12 +135,25 @@ static inline int pstate_enable(bool enable) > > static int cppc_enable(bool enable) > { > + struct cppc_perf_ctrls perf_ctrls; > int cpu, ret = 0; > > for_each_present_cpu(cpu) { > ret = cppc_set_enable(cpu, enable); > if (ret) > return ret; > + if (epp) { > + /* Enable autonomous mode for EPP */ > + ret = cppc_set_auto_epp(cpu, enable); > + if (ret) > + return ret; > + > + /* Set desired perf as zero to allow EPP firmware control */ > + perf_ctrls.desired_perf = 0; > + ret = cppc_set_perf(cpu, &perf_ctrls); > + if (ret) > + return ret; > + } This patch only writes the desired_perf as 0 to enable the EPP function, but it cannot be an independent function or patch without the dependency of the next one (patch 7). Thanks, Ray