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References: <202210072120.V1O2SuKY-lkp@intel.com> <20221010175134.2671410-1-ndesaulniers@google.com>
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From:   Ard Biesheuvel <ardb@kernel.org>
Date:   Mon, 17 Oct 2022 15:49:42 +0200
Message-ID: <CAMj1kXFpBH-aOR47fONFdt3B_w7WkmveD2PcS4AbEE=ZqAHX+A@mail.gmail.com>
Subject: Re: [PATCH] lib/xor: use r10 rather than r7 in xor_arm4regs_{2|3}
To:     Nick Desaulniers <ndesaulniers@google.com>
Cc:     Russell King <linux@armlinux.org.uk>,
        Nathan Chancellor <nathan@kernel.org>,
        Tom Rix <trix@redhat.com>,
        Herbert Xu <herbert@gondor.apana.org.au>,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        llvm@lists.linux.dev,
        "Steven Rostedt (Google)" <rostedt@goodmis.org>,
        kernel test robot <lkp@intel.com>, kbuild-all@lists.01.org
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On Mon, 10 Oct 2022 at 19:51, Nick Desaulniers <ndesaulniers@google.com> wrote:
>
> kbuild test robot reports:
> In file included from crypto/xor.c:17:
> ./arch/arm/include/asm/xor.h:61:3: error: write to reserved register 'R7'
>                 GET_BLOCK_4(p1);
>                 ^
> ./arch/arm/include/asm/xor.h:20:10: note: expanded from macro 'GET_BLOCK_4'
>         __asm__("ldmia  %0, {%1, %2, %3, %4}" \
>                 ^
> ./arch/arm/include/asm/xor.h:63:3: error: write to reserved register 'R7'
>                 PUT_BLOCK_4(p1);
>                 ^
> ./arch/arm/include/asm/xor.h:42:23: note: expanded from macro 'PUT_BLOCK_4'
>         __asm__ __volatile__("stmia     %0!, {%2, %3, %4, %5}" \
>                              ^
> ./arch/arm/include/asm/xor.h:83:3: error: write to reserved register 'R7'
>                 GET_BLOCK_4(p1);
>                 ^
> ./arch/arm/include/asm/xor.h:20:10: note: expanded from macro 'GET_BLOCK_4'
>         __asm__("ldmia  %0, {%1, %2, %3, %4}" \
>                 ^
> ./arch/arm/include/asm/xor.h:86:3: error: write to reserved register 'R7'
>                 PUT_BLOCK_4(p1);
>                 ^
> ./arch/arm/include/asm/xor.h:42:23: note: expanded from macro 'PUT_BLOCK_4'
>         __asm__ __volatile__("stmia     %0!, {%2, %3, %4, %5}" \
>                              ^
> Thumb2 uses r7 rather than r11 as the frame pointer. Let's use r10
> rather than r7 for these temporaries.
>
> Link: https://github.com/ClangBuiltLinux/linux/issues/1732
> Link: https://lore.kernel.org/llvm/202210072120.V1O2SuKY-lkp@intel.com/
> Reported-by: kernel test robot <lkp@intel.com>
> Suggested-by: Ard Biesheuvel <ardb@kernel.org>
> Signed-off-by: Nick Desaulniers <ndesaulniers@google.com>

Reviewed-by: Ard Biesheuvel <ardb@kernel.org>

> ---
>  arch/arm/include/asm/xor.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/asm/xor.h
> index 669cad5194d3..934b549905f5 100644
> --- a/arch/arm/include/asm/xor.h
> +++ b/arch/arm/include/asm/xor.h
> @@ -51,7 +51,7 @@ xor_arm4regs_2(unsigned long bytes, unsigned long * __restrict p1,
>         register unsigned int a1 __asm__("r4");
>         register unsigned int a2 __asm__("r5");
>         register unsigned int a3 __asm__("r6");
> -       register unsigned int a4 __asm__("r7");
> +       register unsigned int a4 __asm__("r10");
>         register unsigned int b1 __asm__("r8");
>         register unsigned int b2 __asm__("r9");
>         register unsigned int b3 __asm__("ip");
> @@ -73,7 +73,7 @@ xor_arm4regs_3(unsigned long bytes, unsigned long * __restrict p1,
>         register unsigned int a1 __asm__("r4");
>         register unsigned int a2 __asm__("r5");
>         register unsigned int a3 __asm__("r6");
> -       register unsigned int a4 __asm__("r7");
> +       register unsigned int a4 __asm__("r10");
>         register unsigned int b1 __asm__("r8");
>         register unsigned int b2 __asm__("r9");
>         register unsigned int b3 __asm__("ip");
> --
> 2.38.0.rc2.412.g84df46c1b4-goog
>