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From:   Siarhei Volkau <lis8215@gmail.com>
Date:   Mon, 17 Oct 2022 21:07:47 +0300
Message-ID: <CAKNVLfbbAaNdhWDo10XrUtyCM4R5E1CidC+TTQt8tUYbBU93qw@mail.gmail.com>
Subject: Re: [PATCH v2 4/4] clk: Add Ingenic JZ4755 CGU driver
To:     Paul Cercueil <paul@crapouillou.net>
Cc:     Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
        linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org
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=D0=BF=D0=BD, 17 =D0=BE=D0=BA=D1=82. 2022 =D0=B3. =D0=B2 20:24, Paul Cercue=
il <paul@crapouillou.net>:
>
>
>
> Le lun., oct. 17 2022 at 20:10:56 +0300, Siarhei Volkau
> <lis8215@gmail.com> a =C3=A9crit :
> > =D0=BF=D0=BD, 17 =D0=BE=D0=BA=D1=82. 2022 =D0=B3. =D0=B2 12:24, Paul Ce=
rcueil
> > <paul@crapouillou.net>:
> >
> >>  > +     [JZ4755_CLK_AIC] =3D {
> >>  > +             "aic", CGU_CLK_GATE,
> >>  > +             .parents =3D { JZ4755_CLK_I2S, -1, -1, -1 },
> >>
> >>  Wrong parent here, should be JZ4755_CLK_EXT_HALF.
> >
> > I don't  agree, see Figure 20-13 in the JZ4755 PM.
>
> 20-13 describes the I2S clock, no?

See 20.4.9 Serial Audio Clocks and Sampling Frequencies.
It stated that: "For internal CODEC ... CODEC needs a 12MHz
clock from CPM called SYS_CLK ...", but SYS_CLK is described
only in the I2S Controller section. I assume it is the same clock.

>
> AIC clock's parent is EXT/2 according to the diagram in 8.2.2.
>

It's a bit cryptic manual, who knows how it's done in the HW.
I observed that codec runs on a desired sample rate only when PLL
equals 432 or 216 MHz, but SYS_CLK is definitely configured to be
12MHz - from EXTCLK. On other PLL frequencies it is lower by
2-4% than expected. That isn't observed on JZ4725B.

> >>  Well it would be good to know...
> >
> > Indeed, I will try to figure it out.
>
> Cheers,
> -Paul
>
>