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Date:   Tue, 18 Oct 2022 09:45:34 +0200
From:   Michael Walle <michael@walle.cc>
To:     Eliav Farber <farbere@amazon.com>
Cc:     tudor.ambarus@microchip.com, pratyush@kernel.org,
        miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com,
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Subject: Re: [PATCH] mtd: spi-nor: micron-st: Enable locking for n25q256ax1
In-Reply-To: <20221018072254.21606-1-farbere@amazon.com>
References: <20221018072254.21606-1-farbere@amazon.com>
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Hi,

Am 2022-10-18 09:22, schrieb Eliav Farber:
> n25q256ax1 [1] uses the 4 bit Block Protection scheme and supports
> Top/Bottom protection via the BP and TB bits of the Status Register.
> BP3 is located in bit 6 of the Status Register.
> Tested on n25q256ax1.
> 
> [1] 
> https://www.micron.com/-/media/client/global/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_256mb_3v.pdf
> 
> Signed-off-by: Eliav Farber <farbere@amazon.com>

Looks good. But could you please dump the SFDP tables as
described in [1].

-michael

[1] 
https://lore.kernel.org/linux-mtd/4304e19f3399a0a6e856119d01ccabe0@walle.cc/