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Date:   Tue, 18 Oct 2022 14:30:57 +0100
From:   Paul Cercueil <paul@crapouillou.net>
Subject: Re: [PATCH v2 4/4] clk: Add Ingenic JZ4755 CGU driver
To:     Siarhei Volkau <lis8215@gmail.com>
Cc:     Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
        linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org
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Hi Siarhei,

Le lun., oct. 17 2022 at 21:07:47 +0300, Siarhei Volkau=20
<lis8215@gmail.com> a =C3=A9crit :
> =D0=BF=D0=BD, 17 =D0=BE=D0=BA=D1=82. 2022 =D0=B3. =D0=B2 20:24, Paul Cerc=
ueil=20
> <paul@crapouillou.net>:
>>=20
>>=20
>>=20
>>  Le lun., oct. 17 2022 at 20:10:56 +0300, Siarhei Volkau
>>  <lis8215@gmail.com> a =C3=A9crit :
>>  > =D0=BF=D0=BD, 17 =D0=BE=D0=BA=D1=82. 2022 =D0=B3. =D0=B2 12:24, Paul =
Cercueil
>>  > <paul@crapouillou.net>:
>>  >
>>  >>  > +     [JZ4755_CLK_AIC] =3D {
>>  >>  > +             "aic", CGU_CLK_GATE,
>>  >>  > +             .parents =3D { JZ4755_CLK_I2S, -1, -1, -1 },
>>  >>
>>  >>  Wrong parent here, should be JZ4755_CLK_EXT_HALF.
>>  >
>>  > I don't  agree, see Figure 20-13 in the JZ4755 PM.
>>=20
>>  20-13 describes the I2S clock, no?
>=20
> See 20.4.9 Serial Audio Clocks and Sampling Frequencies.
> It stated that: "For internal CODEC ... CODEC needs a 12MHz
> clock from CPM called SYS_CLK ...", but SYS_CLK is described
> only in the I2S Controller section. I assume it is the same clock.

Yes, and your SYS_CLK is the I2S clock, not the AIC clock.

>>=20
>>  AIC clock's parent is EXT/2 according to the diagram in 8.2.2.
>>=20
>=20
> It's a bit cryptic manual, who knows how it's done in the HW.
> I observed that codec runs on a desired sample rate only when PLL
> equals 432 or 216 MHz, but SYS_CLK is definitely configured to be
> 12MHz - from EXTCLK. On other PLL frequencies it is lower by
> 2-4% than expected. That isn't observed on JZ4725B.

The audio codec supplies SYS_CLK to the controller, not the other way=20
around. Parent the I2S clock to EXT/2 (which is 12 MHz) and it should=20
work fine, independently of the PLL.

The AIC clock does not drive anything, it only "powers" the AIC module.=20
It should be parented only to EXT/2, similar to what's done in every=20
other CGU driver.

Cheers,
-Paul