Received: by 2002:a05:6358:1087:b0:cb:c9d3:cd90 with SMTP id j7csp134316rwi; Tue, 18 Oct 2022 15:17:48 -0700 (PDT) X-Google-Smtp-Source: AMsMyM64iyksa8aImBok6STaK9CG9M6sHjfvn74VbQ+GdBlqrIbdWUNJ2YcvJmt/QSFNakCFm1Aq X-Received: by 2002:a17:902:db09:b0:185:5440:1ea0 with SMTP id m9-20020a170902db0900b0018554401ea0mr5312354plx.113.1666131468081; Tue, 18 Oct 2022 15:17:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666131468; cv=none; d=google.com; s=arc-20160816; b=zaTF9Olg8ml4TwtIh5JEDDufZexHrbKoXDu8/wA8YeJlELJv0Xl2Rx4RWWESlKs41y ++9kDYQG45cazm4kgDAj+LFvJR2PeZ5ECcT8vqxXLIz/ODpkWRWLHANZF+tv9p7Qfxvu /9RQAPNfvl0mLGo8yT+0ZBEsD+Rx3ccSN6w7rn4yG5QMg73zQYMWKrT7OHWeB7zXH84E s19V/a6qUACqvvCckbVCNWwM9va8zG+vfDH/MmKon/8i7giF7/crxnU/xLnWM/XvSkBt 17wjTdcuoyvrj5Z1McdMr+0gDGIyqVVbaYsk3JQDfv0oqlqP/6BdF6I7lYaAMEQ5XmKm Grlw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=R6zqkZZ4vlbyYhH3cLfodckZJSbY3NvNFnYiPlIDyiw=; b=ZUP5HaZ2ynHQR4U2IsH7dwb9Rn0W2km8v/yd3uMXMkAWJlZfyG5SAaQ612vLZhrIMz 1UiXhWoktc61Znr4jm+gNdTi6m8NuUZ7E1JyN0usJYgLPFvWrB+vD4pyq4WT5b9WCemB AkUsB+aZuaGiKssJaG5ah8RIsUZnfBoomV9a+EaHZjzTzIn2br0QoWno1XYK0Daggvd5 af7fH63eEoeAsNts3FmiKbpusCDMinEQc6VOlVhJFtin61JMQ7jCAh9JmNIH5YkOdVWL oEtC2PxNeXc3+r6pFiDd6W51ICuN4MaIPMIgSxNpbagXHxkzI392Ab/jCmQ0IAp1aFch ioog== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=F3xbhjoB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id oc14-20020a17090b1c0e00b0020c4fd9306bsi23622012pjb.166.2022.10.18.15.17.36; Tue, 18 Oct 2022 15:17:48 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=F3xbhjoB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230341AbiJRVQC (ORCPT + 99 others); Tue, 18 Oct 2022 17:16:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46024 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230255AbiJRVPu (ORCPT ); Tue, 18 Oct 2022 17:15:50 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 200B49187F; Tue, 18 Oct 2022 14:15:48 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 29ILFaQj108206; Tue, 18 Oct 2022 16:15:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1666127736; bh=R6zqkZZ4vlbyYhH3cLfodckZJSbY3NvNFnYiPlIDyiw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=F3xbhjoBAiFJtI7G9+seFKRwTZOo44P+8rfhZWGQpXU+4yKsGzDbtuZEWNnR/9AyB 3H96RI4Cc0cpbNhwecdwQ/m3lnevz0pF4/2daIDB0VzZNoYvIno/wgXTyBBzwyP7Hk /rd7HbtOuw/CPRJnezHyg37NoQRo1WMqSUrl2U1s= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 29ILFa7f005821 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 18 Oct 2022 16:15:36 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Tue, 18 Oct 2022 16:15:36 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Tue, 18 Oct 2022 16:15:36 -0500 Received: from ula0226330.dal.design.ti.com (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 29ILFXoD014456; Tue, 18 Oct 2022 16:15:35 -0500 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Bryan Brattlof , , , CC: Andrew Davis Subject: [PATCH 03/10] arm64: dts: ti: k3-am62: Enable SPI nodes at the board level Date: Tue, 18 Oct 2022 16:15:26 -0500 Message-ID: <20221018211533.21335-4-afd@ti.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221018211533.21335-1-afd@ti.com> References: <20221018211533.21335-1-afd@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org SPI nodes defined in the top-level AM62x SoC dtsi files are incomplete and will not be functional unless they are extended with pinmux information. As the pinmux is only known at the board integration level, these nodes should only be enabled when provided with this information. Disable the SPI nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 3 +++ arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi | 2 ++ 2 files changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index 295c9bb22e7d..83ac2e45998d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -318,6 +318,7 @@ main_spi0: spi@20100000 { #size-cells = <0>; power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 172 0>; + status = "disabled"; }; main_spi1: spi@20110000 { @@ -328,6 +329,7 @@ main_spi1: spi@20110000 { #size-cells = <0>; power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 173 0>; + status = "disabled"; }; main_spi2: spi@20120000 { @@ -338,6 +340,7 @@ main_spi2: spi@20120000 { #size-cells = <0>; power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 174 0>; + status = "disabled"; }; main_gpio_intr: interrupt-controller@a00000 { diff --git a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi index 7f715ebe8e24..28daf476e6a9 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi @@ -44,6 +44,7 @@ mcu_spi0: spi@4b00000 { #size-cells = <0>; power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 147 0>; + status = "disabled"; }; mcu_spi1: spi@4b10000 { @@ -54,6 +55,7 @@ mcu_spi1: spi@4b10000 { #size-cells = <0>; power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 148 0>; + status = "disabled"; }; mcu_gpio_intr: interrupt-controller@4210000 { -- 2.37.3