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Date:   Thu, 20 Oct 2022 10:06:32 +0530
From:   Viresh Kumar <viresh.kumar@linaro.org>
To:     =?utf-8?B?S8O2cnk=?= Maincent <kory.maincent@bootlin.com>
Cc:     linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, thomas.petazzoni@bootlin.com,
        Viresh Kumar <vireshk@kernel.org>,
        Shiraz Hashim <shiraz.linux.kernel@gmail.com>, soc@kernel.org,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Subject: Re: [PATCH 5/6] arm: dts: spear600: Add ssp controller nodes
Message-ID: <20221020043632.cbofx5jvajhy4xba@vireshk-i7>
References: <20221019133208.319626-1-kory.maincent@bootlin.com>
 <20221019133208.319626-6-kory.maincent@bootlin.com>
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On 19-10-22, 15:32, K?ry Maincent wrote:
> From: Kory Maincent <kory.maincent@bootlin.com>
> 
> The SPEAr600 has three Synchronous serial port to enables synchronous
> serial communication with slave or master peripherals (SPI). Lets add these
> nodes to be able to use them.
> 
> Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
> ---
>  arch/arm/boot/dts/spear600.dtsi | 30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
> index 9d5a04a46b14..6b67c0ceaed9 100644
> --- a/arch/arm/boot/dts/spear600.dtsi
> +++ b/arch/arm/boot/dts/spear600.dtsi
> @@ -207,6 +207,36 @@ adc: adc@d820b000 {
>  				interrupts = <6>;
>  				status = "disabled";
>  			};
> +
> +			ssp1: spi@d0100000 {
> +				compatible = "arm,pl022", "arm,primecell";
> +				reg = <0xd0100000 0x1000>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				interrupt-parent = <&vic0>;
> +				interrupts = <26>;
> +				status = "disabled";
> +			};
> +
> +			ssp2: spi@d0180000 {
> +				compatible = "arm,pl022", "arm,primecell";
> +				reg = <0xd0180000 0x1000>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				interrupt-parent = <&vic0>;
> +				interrupts = <27>;
> +				status = "disabled";
> +			};
> +
> +			ssp3: spi@d8180000 {
> +				compatible = "arm,pl022", "arm,primecell";
> +				reg = <0xd8180000 0x1000>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				interrupt-parent = <&vic1>;
> +				interrupts = <5>;
> +				status = "disabled";
> +			};
>  		};
>  	};
>  };

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>

-- 
viresh