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Date:   Thu, 20 Oct 2022 13:12:39 +0200
From:   Marco Felsch <m.felsch@pengutronix.de>
To:     "Peng Fan (OSS)" <peng.fan@oss.nxp.com>
Cc:     robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
        shawnguo@kernel.org, s.hauer@pengutronix.de,
        devicetree@vger.kernel.org, Peng Fan <peng.fan@nxp.com>,
        Frank Li <frank.li@nxp.com>, linux-kernel@vger.kernel.org,
        linux-imx@nxp.com, kernel@pengutronix.de, Han Xu <han.xu@nxp.com>,
        festevam@gmail.com, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 06/15] arm64: dts: imx8mp-evk: enable fspi nor on imx8mp
 evk
Message-ID: <20221020111239.vunok2je26tl2nko@pengutronix.de>
References: <20221020095934.1659449-1-peng.fan@oss.nxp.com>
 <20221020095934.1659449-7-peng.fan@oss.nxp.com>
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Hi Peng,

On 22-10-20, Peng Fan (OSS) wrote:
> From: Han Xu <han.xu@nxp.com>
> 
> enable fspi nor on imx8mp evk dts
> 
> Reviewed-by: Frank Li <frank.li@nxp.com>
> Signed-off-by: Han Xu <han.xu@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 27 ++++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> index 366f709f8790..f36033b9cebb 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> @@ -85,6 +85,22 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
>  	};
>  };
>  
> +&flexspi {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_flexspi0>;
> +	status = "okay";
> +
> +	flash0: mt25qu256aba@0 {
                     ^
This should throw a warning. You need to name it flash@0.
Nit: The phandle name is not very useful, instead I would name it
nor_flash or so.

> +		reg = <0>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "jedec,spi-nor";

compatible is the first property followed by the reg.

> +		spi-max-frequency = <80000000>;
> +		spi-tx-bus-width = <1>;
> +		spi-rx-bus-width = <4>;
> +	};
> +};
> +
>  &A53_0 {
>  	cpu-supply = <&reg_arm>;
>  };
> @@ -585,6 +601,17 @@ MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27      0x154   /* CAN2_STBY */
>  		>;
>  	};
>  
> +	pinctrl_flexspi0: flexspi0grp {
> +		fsl,pins = <
> +			MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK           0x1c2
> +			MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B        0x82
> +			MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00      0x82
> +			MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01      0x82
> +			MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02      0x82
> +			MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03      0x82
> +		>;
> +	};
> +
>  	pinctrl_gpio_led: gpioledgrp {
>  		fsl,pins = <
>  			MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16	0x140
> -- 
> 2.37.1
> 
> 
>