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Date:   Fri, 21 Oct 2022 11:53:33 +0200
From:   Marco Felsch <m.felsch@pengutronix.de>
To:     Peng Fan <peng.fan@oss.nxp.com>
Cc:     robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
        shawnguo@kernel.org, s.hauer@pengutronix.de,
        devicetree@vger.kernel.org, Peng Fan <peng.fan@nxp.com>,
        linux-kernel@vger.kernel.org, linux-imx@nxp.com,
        kernel@pengutronix.de, festevam@gmail.com,
        linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 05/15] arm64: dts: imx8mp-evk: enable uart1/3 ports
Message-ID: <20221021095333.3qdqtdstgcjhp76s@pengutronix.de>
References: <20221020095934.1659449-1-peng.fan@oss.nxp.com>
 <20221020095934.1659449-6-peng.fan@oss.nxp.com>
 <20221020110723.udftsfrfdnghudto@pengutronix.de>
 <7ede9de4-75ba-6ebf-60a3-fee98e050ea9@oss.nxp.com>
 <20221021090910.zkijqqt6mpukzqdp@pengutronix.de>
 <5ddc1dac-b6ee-34c4-63eb-63c9a254d984@oss.nxp.com>
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On 22-10-21, Peng Fan wrote:
> Hi Marco,
> 
> On 10/21/2022 5:09 PM, Marco Felsch wrote:
> > On 22-10-21, Peng Fan wrote:
> > > Hi Marco,
> > > 
> > > On 10/20/2022 7:07 PM, Marco Felsch wrote:
> > > > Hi Peng,
> > > > 
> > > > On 22-10-20, Peng Fan (OSS) wrote:
> > > > > From: Peng Fan <peng.fan@nxp.com>
> > > > > 
> > > > > Enable uart1/3 ports for evk board.
> > > > > 
> > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > > ---
> > > > >    arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 36 ++++++++++++++++++++
> > > > >    1 file changed, 36 insertions(+)
> > > > > 
> > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > > > > index 2e29bb3c041c..366f709f8790 100644
> > > > > --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > > > > +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > > > > @@ -428,6 +428,15 @@ &snvs_pwrkey {
> > > > >    	status = "okay";
> > > > >    };
> > > > > +&uart1 { /* BT */
> > > > > +	pinctrl-names = "default";
> > > > > +	pinctrl-0 = <&pinctrl_uart1>;
> > > > > +	assigned-clocks = <&clk IMX8MP_CLK_UART1>;
> > > > > +	assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
> > > > 
> > > > I'm curious, what is the default parent and why is this wrong? For the
> > > > already exisiting uart2 we don't do that. Same applies for uart3.
> > > 
> > > The default parent is OSC_24M. The uart2 is for console, so 24M is ok.
> > > As I recall, we met issue 24M not able to get higher baudrate.
> > 
> > What did you mean by higher baudrate, is it everything > 115200? When
> > the console baudrates can be fullfilled with the PLL1_80M as well
> > wouldn't it be worth to fix the imx8mp.dtsi instead?
> 
> To console, we use 115200, 24M could fullfill it.
> 
> BaudRate = (clk / ref_clk_div) / (16 * (ubmr + 1) / (ubir + 1))
> 
> If you have 24M ref_clk, the max baudrate is 1.5M, with setting
> ubmr, ubir to 0, and ref clk divider to 1.
> 
> So more higher baudrate, 24M could not fulfill.

Okay, thanks for clarification. In that case eveything is fine.

Regards,
  Marco