Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
From:   "Tilki, Ibrahim" <Ibrahim.Tilki@analog.com>
To:     Alexandre Belloni <alexandre.belloni@bootlin.com>
CC:     "a.zummo@towertech.it" <a.zummo@towertech.it>,
        "jdelvare@suse.com" <jdelvare@suse.com>,
        "linux@roeck-us.net" <linux@roeck-us.net>,
        "robh+dt@kernel.org" <robh+dt@kernel.org>,
        "krzysztof.kozlowski+dt@linaro.org" 
        <krzysztof.kozlowski+dt@linaro.org>,
        "linux-rtc@vger.kernel.org" <linux-rtc@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "linux-hwmon@vger.kernel.org" <linux-hwmon@vger.kernel.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "Arslanbenzer, Zeynep" <Zeynep.Arslanbenzer@analog.com>
Subject: RE: [PATCH 2/2] dt-bindings: rtc: add bindings for max313xx RTCs
Thread-Topic: [PATCH 2/2] dt-bindings: rtc: add bindings for max313xx RTCs
Thread-Index: AQHY48BZbMpT/SjNa0SzYqltq8qQ864XyjkAgADySLCAAA2cAIAACL6g
Date:   Fri, 21 Oct 2022 13:05:44 +0000
Message-ID: <DM8PR03MB6247691C7AD890FA486A5955962D9@DM8PR03MB6247.namprd03.prod.outlook.com>
References: <20221019133910.282-1-Ibrahim.Tilki@analog.com>
 <20221019133910.282-2-Ibrahim.Tilki@analog.com> <Y1G6FIvS6WD57GXW@mail.local>
 <DM8PR03MB62477670C186E6CC5308B600962D9@DM8PR03MB6247.namprd03.prod.outlook.com>
 <Y1KQvPAwh7NC0wbA@mail.local>
In-Reply-To: <Y1KQvPAwh7NC0wbA@mail.local>
Accept-Language: en-US
Content-Language: en-US
x-ms-exchange-antispam-messagedata-chunkcount: 1
x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?rY30AfFhThKZSj7Xr4iHFZOVRXBlv22S8VwO86mCbT6x9CA7zBEOVGbRCf23?=
 =?us-ascii?Q?W1T2+mUMiwUY3O1dFa7uACslkjtmuUhJENMahk8NeqtUkaF8jnoz9Nu9TIjo?=
 =?us-ascii?Q?bDGl9rducFt8gzJoPLxjnY4T2biqQ9HvGmsOUxRSuC9X0+LVlffeNXpwTLEi?=
 =?us-ascii?Q?r92Jw9djspx8URBgCFWWqS34DCL/pZb3RmAacXkn5zDo96Jk49HU5SvrEuc9?=
 =?us-ascii?Q?/BqzKrB3AKveJiaPuQq7QltHdbMfjlDGUb1MH2YabZb+ZNj8KfkT5auZRklG?=
 =?us-ascii?Q?dYbSIxXKp0uV506BXjlRUXhPW32in71RxrXfFXcUYrDD2j0eLCpzubyVti4V?=
 =?us-ascii?Q?Woot4PtOUFukjxBoDLYgK6pyrZ3T62DNDnk0amCyBc9/UxdbwSMdTO4cmafn?=
 =?us-ascii?Q?jnayt5IG1KrfIupmBCkHhOtk3VRVLxTag7JVB8VCwvK0Hn+6lKJaSJcdnBzX?=
 =?us-ascii?Q?wcmDrN6AVj1bTe8YIucSwJMWcXZeadC2L87VRYgTxCdEoGy2EiebBI3XhmKV?=
 =?us-ascii?Q?8SGRYOPZWKnWH1eIHyI6VAYX/tBEVtHIIRMrmMgSgEwRO50AxJfjeNeestIo?=
 =?us-ascii?Q?2oa56tFJZTdIU4c/EwHV+rBlvPQTNCStktUV+IXZ7YUUwHFqhiddQWg23OHt?=
 =?us-ascii?Q?fOHsbWAPSL9Q9ZbLmVgH7GpUjEdL5OlxtKhEwrpZpWojz735HMvjmDdImrnE?=
 =?us-ascii?Q?VNQLhw/sTB6pPyx5q/hnkbrMlbBoFDtzkqMtTOOZifXCmLN9sql1YH0GdBhA?=
 =?us-ascii?Q?UmEcGNO3KxC/4t7Ncbihr8aABdyJdROl9yK9FnJoonJ3h5MJu4jXtNu6BAUD?=
 =?us-ascii?Q?LgWFB3StcJvaPMueDTPmQ2BdX87+Sujbku9/NU95YFqJuoKa7xzTQEojgCxJ?=
 =?us-ascii?Q?xaT/XxdhvjoSDD3zUsTIQuCHgO2RtEulsGmbt2A2NKXRKRBU+8F6Ko03OaPI?=
 =?us-ascii?Q?obeVjnaL6NqfaJ2jOcTRIc59NyZosvtlTuN3JP9mbse/q6gRhAYLJjV0GdzY?=
 =?us-ascii?Q?aGi4/t2Xvnz2sDhwnAtzM+q88p57K3lVAij76+DaexjaF/pD6R4DOGI8k39z?=
 =?us-ascii?Q?d9ya2/6UbAMLFxgsnuX9qIzDAlSRFOcSPCQqMNMFKKTQwQlJ40pEJ2xj+IIB?=
 =?us-ascii?Q?v3OPjPdOZBEOmYZqnan6gLOlLacBnZDAqinXZkWZSL+mdHbuC9RPDIsHyy+b?=
 =?us-ascii?Q?ExwuSqWL+TYE37ezFsSSzcMFKANMpWpFundR9DKZIAjgGuP+McbjZlNnd1GI?=
 =?us-ascii?Q?d5t0RU+ruq6nq3q1HEAIeTm6Zjqw9iRnPd57KEpbbfN64kU5cnk4dAIpatXl?=
 =?us-ascii?Q?N67KARHyL58L4uYZigJu7s7cJc7WKWdVY0BAQgQMOwZsTB2iIMMakDxuhK9s?=
 =?us-ascii?Q?6mFw1Bx21ltVPR74kuHyDeVLYNcDDTubMy0yrPQ6FRQ50IR/mBJTsy4uv8vI?=
 =?us-ascii?Q?isVJmZlcYRqc6rR3m3+B2pEmXRTTFbf/TWgt6t3rz95VI7VHy85XpWTiCd1g?=
 =?us-ascii?Q?2ru2MCwRMb9lFfsluKTHo3RDHhxS7wPiI5gN4ocJ9OQFkp4D9UrNiEfkuwIR?=
 =?us-ascii?Q?lniSlIzH9hNCz4MAturqjBJvlPJZKuCVT5IRPLRh?=
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
MIME-Version: 1.0
X-OriginatorOrg: analog.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-AuthSource: DM8PR03MB6247.namprd03.prod.outlook.com
X-MS-Exchange-CrossTenant-Network-Message-Id: 2fb04e91-5376-4b8a-fc3b-08dab364f6aa
X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Oct 2022 13:05:44.2380
 (UTC)
X-MS-Exchange-CrossTenant-fromentityheader: Hosted
X-MS-Exchange-CrossTenant-id: eaa689b4-8f87-40e0-9c6f-7228de4d754a
X-MS-Exchange-CrossTenant-mailboxtype: HOSTED
X-MS-Exchange-CrossTenant-userprincipalname: NwbDKiYjrKGDENRmiav/q7WTLtcMc8J2ZOKSxEh9h++NuNIMITKCO3VNvVEBK+i91RKbYwGjrlm9Ra5Cm0zBlAm+8yYL849hr7Qgd3ST0PI=
X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR03MB5598
X-Proofpoint-GUID: -rnlGM5ZSuD7N9AjFPZamTG0_984jlCd
X-Proofpoint-ORIG-GUID: -rnlGM5ZSuD7N9AjFPZamTG0_984jlCd
X-Proofpoint-Virus-Version: vendor=baseguard
 engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1
 definitions=2022-10-21_04,2022-10-21_01,2022-06-22_01
X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0
 priorityscore=1501 clxscore=1015 phishscore=0 bulkscore=0 impostorscore=0
 mlxscore=0 malwarescore=0 spamscore=0 mlxlogscore=892 adultscore=0
 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1
 engine=8.12.0-2209130000 definitions=main-2210210078
X-Spam-Status: No, score=-2.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,
        DKIM_VALID,RCVD_IN_DNSWL_LOW,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS
        autolearn=ham autolearn_force=no version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on
        lindbergh.monkeyblade.net
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

> On 21/10/2022 11:44:12+0000, Tilki, Ibrahim wrote:
> > > > +  interrupt-names:
> > > > +    description: |
> > > > +      Name of the interrupt pin of the RTC used for IRQ. Not requi=
red for
> > > > +      RTCs that only have single interrupt pin available. Some of =
the RTCs
> > > > +      share interrupt pins with clock input/output pins.
> > > > +    minItems: 1
> > > > +    items:
> > > > +      - enum: [INTA, INTB]
> > > > +      - enum: [INTA, INTB]
> > > > +
> > >=20
> > > I don't think this is right, what this is doing is essentially pinmux=
ing
> > > interrupts versus clocks. What happens if you want INTB but this goes
> > > directly to a PMIC instead of the SoC?
> > > It is not something you can express with your current bindings.
> > >=20
> >=20
> > Why would a user want INTB when it is not connected to SoC?
> > User can specify none, either one or both of the interrupt pins.
> > I don't see what the problem here is.
> >=20
>=20
> the interrupt pin may be connected to a PMIC that is able to start or
> wake up the platform. In that case, the user would not have any
> interrupt-names and your driver will fail to mux the interrupt on INTB.
> Please fix.

Interrupt muxing depends on the clock configuration, not the interrupt-name=
s property.
Devices don't support muxing the alarm interrupt independently.

For example in the case of max31329, alarm interrupt is muxed into INTA by =
default.
Alarm interrupt is muxed into INTB pin if and only if clkin is enabled.

This means that if a user wants the alarm interrupt on INTB pin, they have =
to
provide a clock input through "clocks" property. If that is the case, they =
can provide
an interrupt for INTB pin, otherwise the alarm feature of the rtc gets disa=
bled.

Side note: Some devices have 2 Alarms but Alarm2 does not have a register f=
or
matching "seconds" so only Alarm1 is used by the driver.

Ibrahim