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Message-ID: <389dc5e4-1785-80b3-3798-f54f4b51be81@kernel.org>
Date:   Fri, 21 Oct 2022 10:17:18 -0500
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Subject: Re: [PATCHv5 4/6] mmc: dw_mmc-pltfm: socfpga: add method to configure
 clk-phase
To:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        jh80.chung@samsung.com
Cc:     ulf.hansson@linaro.org, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com,
        sboyd@kernel.org, linux-mmc@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-clk@vger.kernel.org
References: <20221019170657.68014-1-dinguyen@kernel.org>
 <20221019170657.68014-5-dinguyen@kernel.org>
 <b74f37ba-d2e3-ab73-a035-739ffb2b0334@linaro.org>
Content-Language: en-US
From:   Dinh Nguyen <dinguyen@kernel.org>
In-Reply-To: <b74f37ba-d2e3-ab73-a035-739ffb2b0334@linaro.org>
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On 10/21/22 08:32, Krzysztof Kozlowski wrote:
> On 19/10/2022 13:06, Dinh Nguyen wrote:
>> The clock-phase settings for the SDMMC controller in the SoCFPGA
>> platforms reside in a register in the System Manager. Add a method
>> to access that register through the syscon interface.
>>
>> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
>> ---
>> v5: change error handling from of_property_read_variable_u32_array()
>>      support arm32 by reading the reg_shift
>> v4: no change
>> v3: add space before &socfpga_drv_data
>> v2: simplify clk-phase calculations
>> ---
>>   drivers/mmc/host/dw_mmc-pltfm.c | 43 ++++++++++++++++++++++++++++++++-
>>   1 file changed, 42 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c
>> index 9901208be797..74421d13f466 100644
>> --- a/drivers/mmc/host/dw_mmc-pltfm.c
>> +++ b/drivers/mmc/host/dw_mmc-pltfm.c
>> @@ -17,10 +17,16 @@
>>   #include <linux/mmc/host.h>
>>   #include <linux/mmc/mmc.h>
>>   #include <linux/of.h>
>> +#include <linux/mfd/altera-sysmgr.h>
>> +#include <linux/regmap.h>
>>   
>>   #include "dw_mmc.h"
>>   #include "dw_mmc-pltfm.h"
>>   
>> +#define SOCFPGA_DW_MMC_CLK_PHASE_STEP	45
>> +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel, reg_shift) \
>> +	((((smplsel) & 0x7) << reg_shift) | (((drvsel) & 0x7) << 0))
>> +
>>   int dw_mci_pltfm_register(struct platform_device *pdev,
>>   			  const struct dw_mci_drv_data *drv_data)
>>   {
>> @@ -62,9 +68,44 @@ const struct dev_pm_ops dw_mci_pltfm_pmops = {
>>   };
>>   EXPORT_SYMBOL_GPL(dw_mci_pltfm_pmops);
>>   
>> +static int dw_mci_socfpga_priv_init(struct dw_mci *host)
>> +{
>> +	struct device_node *np = host->dev->of_node;
>> +	struct regmap *sys_mgr_base_addr;
>> +	u32 clk_phase[2] = {0}, reg_offset, reg_shift;
>> +	int i, rc, hs_timing;
>> +
>> +	rc = of_property_read_variable_u32_array(np, "clk-phase-sd-hs", &clk_phase[0], 2, 0);
>> +	if (rc < 0) {
>> +		dev_err(host->dev, "clk-phase-sd-hs not found!\n");
>> +		return rc;
>> +	}
>> +
>> +	sys_mgr_base_addr = altr_sysmgr_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon");
>> +	if (IS_ERR(sys_mgr_base_addr)) {
>> +		dev_err(host->dev, "failed to find altr,sys-mgr regmap!\n");
>> +		return -ENODEV;
> 
> Isn't this now an ABI break? I have an impression we talked about this...
> 

My fault, I'll make this optional.

Dinh