Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1763306AbXHAJ1u (ORCPT ); Wed, 1 Aug 2007 05:27:50 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1757232AbXHAJ1j (ORCPT ); Wed, 1 Aug 2007 05:27:39 -0400 Received: from ecfrec.frec.bull.fr ([129.183.4.8]:43958 "EHLO ecfrec.frec.bull.fr" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756624AbXHAJ1h (ORCPT ); Wed, 1 Aug 2007 05:27:37 -0400 Message-ID: <46B05209.4050103@bull.net> Date: Wed, 01 Aug 2007 11:27:37 +0200 From: Zoltan Menyhart User-Agent: Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.7.3) Gecko/20040913 X-Accept-Language: en-us, en, fr, hu MIME-Version: 1.0 To: Jim Hull Cc: "'KAMEZAWA Hiroyuki'" , "'David Mosberger-Tang'" , "'LKML'" , linux-ia64@vger.kernel.org, tony.luck@intel.com, "'Christoph Lameter'" Subject: Re: [PATCH] flush icache before set_pte take6. [4/4] optimization for cpus other than montecito References: <20070731113543.93ffd964.kamezawa.hiroyu@jp.fujitsu.com><20070731114155.5785123c.kamezawa.hiroyu@jp.fujitsu.com> <20070731132932.8e21d48c.kamezawa.hiroyu@jp.fujitsu.com> <019b01c7d395$27d692b0$3e3af40f@americas.hpqcorp.net> In-Reply-To: <019b01c7d395$27d692b0$3e3af40f@americas.hpqcorp.net> X-MIMETrack: Itemize by SMTP Server on ECN002/FR/BULL(Release 5.0.12 |February 13, 2003) at 01/08/2007 11:32:18, Serialize by Router on ECN002/FR/BULL(Release 5.0.12 |February 13, 2003) at 01/08/2007 11:32:25, Serialize complete at 01/08/2007 11:32:25 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset=us-ascii; format=flowed Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1082 Lines: 29 Jim Hull wrote: > Not just crazy, but wrong - this *can* happen on pre-Montecito. Even though > L1D is write-through and L2 was mixed I/D, the L1 I-cache could contain > stale instrutions if there are missing flushes. I cannot agree with you. In order to consider an L1 I-cache entry as valid, a corresponding virtual -> physic address translation should be valid in one of the L1 ITLBs. "See 6.1.1. Instruction TLBS" of the I2 Proc. Ref. Man. for SW Dev. & Opt. You cannot have a valid L1 ITLB entry unless you have a corresponding valid L2 ITLB entry. When you remove a PTE (or switch off the exec bit) and you flush the L2 ITLB matching the old translation (and you kill the corresponding L1 ITLBs), you do invalidate the corresponding L1 I-cache entries. Therefore CPU models without split L2 caches are safe. Thanks, Zoltan - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/