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([2a05:6e02:1041:c10:25b:e73e:85eb:ae6e]) by smtp.googlemail.com with ESMTPSA id hp21-20020a1709073e1500b0079800b8173asm3338667ejc.158.2022.10.22.04.12.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 22 Oct 2022 04:12:24 -0700 (PDT) Message-ID: <2b0fe8c2-674a-3b44-16aa-d3008b1271c3@linaro.org> Date: Sat, 22 Oct 2022 13:12:22 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH 1/2] thermal: rockchip: Support RK3588 SoC in the thermal driver Content-Language: en-US To: Nicolas Frattaroli , Sebastian Reichel , Heiko Stuebner , "Rafael J. Wysocki" , Amit Kucheria , Zhang Rui , linux-rockchip@lists.infradead.org Cc: Rob Herring , Krzysztof Kozlowski , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Finley Xiao , kernel@collabora.com References: <20221021174721.92468-1-sebastian.reichel@collabora.com> <20221021174721.92468-2-sebastian.reichel@collabora.com> <2aafa6cc-a7de-0b7a-571f-04593ad53787@linaro.org> <7276280.TLKafQO6qx@archbook> From: Daniel Lezcano In-Reply-To: <7276280.TLKafQO6qx@archbook> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 22/10/2022 10:43, Nicolas Frattaroli wrote: [ ... ] >> What is TOP and CENTER ? >> >> There are 4 Bigs on this platform but two sensors ? > > As far as I know, the four big cores in the SoC are arranged in two > clusters of two cores each, so one temperature sensor for each > cluster. As far as I can tell each CPU in a cluster shares its voltage > with its partner CPU core in its cluster. Ok, I found some more details on the datasheet, page 7-8. So it is a big "Cluster" with the 4 Big cores. They share the same cache. There is one power domain per core (cpuidle) There are two performance domains (cpufreq x 2) So it makes sense to have one sensor per performance domain to mitigate the temperature. > If you have access to the TRM, it contains the following line in > part 1 on page 1372: Unfortunately no, I don't have access to the TRM. But I'll be happy if I can ;) > Support to 7 channel TS-ADC (near chip center, A76_0/1, A76_2/3, > DSU and A55_0/1/2/3, PD_CENTER, NPU, GPU) > > I assume one of "TOP" and "CENTER" is "near chip center", the other is > PD_CENTER, whatever that means (PD = power domain maybe?) Yes certainly. I take the opportunity to let you know there is a new tool in the linux tools directory called 'thermometer'. You can capture the temperature and use the data to create graphics. > I agree these could be named more descriptively. > -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog