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From:   Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
To:     Zhou Yanjie <zhouyu@wanyeetech.com>
Cc:     Paul Cercueil <paul@crapouillou.net>, lgirdwood@gmail.com,
        broonie@kernel.org, perex@perex.cz, tiwai@suse.com,
        linux-mips@vger.kernel.org, alsa-devel@alsa-project.org,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 07/11] ASoC: jz4740-i2s: Make the PLL clock name
 SoC-specific
In-reply-to: <6f2c7a0b-b68b-fc42-1a82-2b69c114823f@wanyeetech.com>
Date:   Sat, 22 Oct 2022 18:15:05 +0100
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Zhou Yanjie <zhouyu@wanyeetech.com> writes:

> Hi Paul,
>
> On 2022/7/13 =E4=B8=8B=E5=8D=8811:07, Paul Cercueil wrote:
>> Hi Zhou,
>>
>> Le mer., juil. 13 2022 at 22:33:44 +0800, Zhou Yanjie <zhouyu@wanyeetech=
.com>
>> a =C3=A9crit :
>>> Hi Aidan,
>>>
>>> On 2022/7/9 =E4=B8=8A=E5=8D=8812:02, Aidan MacDonald wrote:
>>>> @@ -400,6 +402,7 @@ static const struct i2s_soc_info jz4740_i2s_soc_in=
fo =3D
>>>> {
>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 .field_tx_fifo_thresh=C2=A0=C2=A0=C2=A0=
 =3D REG_FIELD(JZ_REG_AIC_CONF, 8, 11),
>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 .field_i2sdiv_capture=C2=A0=C2=A0=C2=A0=
 =3D REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3),
>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 .field_i2sdiv_playback=C2=A0=C2=A0=C2=
=A0 =3D REG_FIELD(JZ_REG_AIC_CLK_DIV, 0, 3),
>>>> +=C2=A0=C2=A0=C2=A0 .pll_clk_name=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0 =3D "pll half",
>>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 .shared_fifo_flush=C2=A0=C2=A0=C2=A0 =
=3D true,
>>>> =C2=A0 };
>>>
>>>
>>> Since JZ4760, according to the description of the I2SCDR register,
>>> Ingenic SoCs no longer use PLL/2 clock, but directly use PLL clock,
>>> so it seems also inappropriate to use "pll half" for these SoCs.
>>
>> The device tree passes the clock as "pll half". So the driver should use=
 this
>> name as well...
>
>
> I see...
>
> It seems that the device tree of JZ4770 has used "pll half" already,
> but there is no "pll half" used anywhere in the device tree of JZ4780,
> maybe we can keep the pll_clk_name of JZ4770 as "pll half", and change
> the pll_clk_name of JZ4780 to a more reasonable name.
>
>
> Thanks and best regards!

Actually, the clock names in the DT are meaningless. The clk_get() call
matches only the clock's name in the CGU driver. So in fact the driver
is "broken" for jz4780. It seems jz4770 doesn't work correctly either,
it has no "pll half", and three possible parents for its "i2s" clock.

Since the driver only supports the internal codec, which requires the
"ext" clock, there isn't a problem in practice.

I'm just going to drop this patch and leave .set_sysclk() alone for now.
I think a better approach is to have the DT define an array of parent
clocks for .set_sysclk()'s use, instead of hardcoding parents in the
driver. If the parent array is missing the driver can default to using
"ext" so existing DTs will work.

Regards,
Aidan