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Date:   Sat, 22 Oct 2022 15:06:54 -0700
From:   Dan Williams <dan.j.williams@intel.com>
To:     Davidlohr Bueso <dave@stgolabs.net>, <dan.j.williams@intel.com>
CC:     <ira.weiny@intel.com>, <Jonathan.Cameron@huawei.com>,
        <dave.jiang@intel.com>, <alison.schofield@intel.com>,
        <bwidawsk@kernel.org>, <vishal.l.verma@intel.com>,
        <a.manzanares@samsung.com>, <linux-cxl@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <dave@stgolabs.net>
Subject: RE: [PATCH 2/2] cxl/mbox: Wire up irq support
Message-ID: <6354697ee26aa_14192942@dwillia2-mobl3.amr.corp.intel.com.notmuch>
References: <20221018030010.20913-1-dave@stgolabs.net>
 <20221018030010.20913-3-dave@stgolabs.net>
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Davidlohr Bueso wrote:
> With enough vectors properly allocated, this adds support for
> (the primary) mailbox interrupt, which is needed for background
> completion handling, beyond polling.
> 
> Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
> ---
>  drivers/cxl/cxl.h |  1 +
>  drivers/cxl/pci.c | 29 ++++++++++++++++++++++++++++-
>  2 files changed, 29 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index f680450f0b16..13a9743b0012 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -135,6 +135,7 @@ static inline int ways_to_cxl(unsigned int ways, u8 *iw)
>  /* CXL 2.0 8.2.8.4 Mailbox Registers */
>  #define CXLDEV_MBOX_CAPS_OFFSET 0x00
>  #define   CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK GENMASK(4, 0)
> +#define   CXLDEV_MBOX_CAP_IRQ_MSGNUM_MASK GENMASK(10, 7)
>  #define CXLDEV_MBOX_CTRL_OFFSET 0x04
>  #define   CXLDEV_MBOX_CTRL_DOORBELL BIT(0)
>  #define CXLDEV_MBOX_CMD_OFFSET 0x08
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 9c3e95ebaa26..c3f3ee307d7a 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -274,6 +274,32 @@ static int cxl_pci_setup_mailbox(struct cxl_dev_state *cxlds)
>  	return 0;
>  }
>  
> +static int cxl_pci_mbox_get_max_msgnum(struct cxl_dev_state *cxlds)
> +{
> +	int cap;
> +
> +	cap = readl(cxlds->regs.mbox + CXLDEV_MBOX_CAPS_OFFSET);
> +	return FIELD_GET(CXLDEV_MBOX_CAP_IRQ_MSGNUM_MASK, cap);
> +}
> +
> +static irqreturn_t cxl_pci_mbox_irq(int irq, void *id)
> +{
> +	/* TODO: handle completion of background commands */
> +	return IRQ_HANDLED;
> +}
> +
> +static void cxl_pci_mbox_irqsetup(struct cxl_dev_state *cxlds)
> +{
> +	struct device *dev = cxlds->dev;
> +	struct pci_dev *pdev = to_pci_dev(dev);
> +	int irq;
> +
> +	irq = cxl_pci_mbox_get_max_msgnum(cxlds);

In this context cxl_pci_mbox_get_max_msgnum() looks misnamed. There is
no max, it's only *the* message number for the mailbox.

> +	if (!pci_request_irq(pdev, irq, cxl_pci_mbox_irq, NULL,
> +			     cxlds, "%s-mailbox", dev_name(dev)))
> +		dev_dbg(dev, "Mailbox irq (%d) supported", irq);
> +}
> +
>  static int cxl_map_regblock(struct pci_dev *pdev, struct cxl_register_map *map)
>  {
>  	void __iomem *addr;
> @@ -442,7 +468,7 @@ struct cxl_irq_cap {
>  };
>  
>  static const struct cxl_irq_cap cxl_irq_cap_table[] = {
> -	NULL
> +	{ "mailbox", cxl_pci_mbox_get_max_msgnum },
>  };
>  
>  static void cxl_pci_free_irq_vectors(void *data)
> @@ -562,6 +588,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
>  		return rc;
>  
>  	if (!cxl_pci_alloc_irq_vectors(cxlds)) {
> +		cxl_pci_mbox_irqsetup(cxlds);
>  		cxlds->has_irq = true;
>  	} else
>  		cxlds->has_irq = false;
> -- 
> 2.38.0
>