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Date:   Sun, 23 Oct 2022 16:20:53 +0100
From:   Paul Cercueil <paul@crapouillou.net>
Subject: Re: [PATCH v1 1/5] clk: ingenic: Make PLL clock "od" field optional
To:     Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Cc:     mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, zhouyu@wanyeetech.com,
        linux-mips@vger.kernel.org, linux-clk@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
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        <20221023145653.177234-2-aidanmacdonald.0x0@gmail.com>
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Hi Aidan,

Le dim. 23 oct. 2022 =E0 15:56:49 +0100, Aidan MacDonald=20
<aidanmacdonald.0x0@gmail.com> a =E9crit :
> Add support for defining PLL clocks with od_bits =3D 0, meaning that
> OD is fixed to 1 and there is no OD field in the register.
>=20
> Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
> ---
>  drivers/clk/ingenic/cgu.c | 28 +++++++++++++++++++---------
>  drivers/clk/ingenic/cgu.h |  3 ++-
>  2 files changed, 21 insertions(+), 10 deletions(-)
>=20
> diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c
> index 861c50d6cb24..7dc2e2567d53 100644
> --- a/drivers/clk/ingenic/cgu.c
> +++ b/drivers/clk/ingenic/cgu.c
> @@ -96,8 +96,11 @@ ingenic_pll_recalc_rate(struct clk_hw *hw,=20
> unsigned long parent_rate)
>  	m +=3D pll_info->m_offset;
>  	n =3D (ctl >> pll_info->n_shift) & GENMASK(pll_info->n_bits - 1, 0);
>  	n +=3D pll_info->n_offset;
> -	od_enc =3D ctl >> pll_info->od_shift;
> -	od_enc &=3D GENMASK(pll_info->od_bits - 1, 0);
> +
> +	if (pll_info->od_bits > 0) {
> +		od_enc =3D ctl >> pll_info->od_shift;
> +		od_enc &=3D GENMASK(pll_info->od_bits - 1, 0);
> +	}
>=20
>  	if (pll_info->bypass_bit >=3D 0) {
>  		ctl =3D readl(cgu->base + pll_info->bypass_reg);
> @@ -108,12 +111,17 @@ ingenic_pll_recalc_rate(struct clk_hw *hw,=20
> unsigned long parent_rate)
>  			return parent_rate;
>  	}
>=20
> -	for (od =3D 0; od < pll_info->od_max; od++) {
> -		if (pll_info->od_encoding[od] =3D=3D od_enc)
> -			break;
> +	if (pll_info->od_bits > 0) {
> +		for (od =3D 0; od < pll_info->od_max; od++) {
> +			if (pll_info->od_encoding[od] =3D=3D od_enc)
> +				break;
> +		}
> +		BUG_ON(od =3D=3D pll_info->od_max);
> +		od++;
> +	} else {
> +		/* OD is fixed to 1 if no OD field is present. */
> +		od =3D 1;
>  	}
> -	BUG_ON(od =3D=3D pll_info->od_max);
> -	od++;

I think if pll_info->od_max is 0 you get the same result without=20
modifying this code. You just need to modify the BUG_ON() to only=20
trigger if pll_info->od_max > 0.

Cheers,
-Paul

>=20
>  	return div_u64((u64)parent_rate * m * pll_info->rate_multiplier,
>  		n * od);
> @@ -215,8 +223,10 @@ ingenic_pll_set_rate(struct clk_hw *hw, unsigned=20
> long req_rate,
>  	ctl &=3D ~(GENMASK(pll_info->n_bits - 1, 0) << pll_info->n_shift);
>  	ctl |=3D (n - pll_info->n_offset) << pll_info->n_shift;
>=20
> -	ctl &=3D ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift);
> -	ctl |=3D pll_info->od_encoding[od - 1] << pll_info->od_shift;
> +	if (pll_info->od_bits > 0) {
> +		ctl &=3D ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift);
> +		ctl |=3D pll_info->od_encoding[od - 1] << pll_info->od_shift;
> +	}
>=20
>  	writel(ctl, cgu->base + pll_info->reg);
>=20
> diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h
> index 147b7df0d657..567142b584bb 100644
> --- a/drivers/clk/ingenic/cgu.h
> +++ b/drivers/clk/ingenic/cgu.h
> @@ -33,7 +33,8 @@
>   * @od_shift: the number of bits to shift the post-VCO divider value=20
> by (ie.
>   *            the index of the lowest bit of the post-VCO divider=20
> value in
>   *            the PLL's control register)
> - * @od_bits: the size of the post-VCO divider field in bits
> + * @od_bits: the size of the post-VCO divider field in bits, or 0 if=20
> no
> + *	     OD field exists (then the OD is fixed to 1)
>   * @od_max: the maximum post-VCO divider value
>   * @od_encoding: a pointer to an array mapping post-VCO divider=20
> values to
>   *               their encoded values in the PLL control register,=20
> or -1 for
> --
> 2.38.1
>=20