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Date:   Mon, 24 Oct 2022 12:01:00 +0300
From:   Dan Carpenter <dan.carpenter@oracle.com>
To:     kbuild@lists.01.org, Yang Li <yang.lee@linux.alibaba.com>
Cc:     lkp@intel.com, kbuild-all@lists.01.org,
        linux-kernel@vger.kernel.org,
        Alex Deucher <alexander.deucher@amd.com>
Subject: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:3047
 commit_planes_for_stream() error: we previously assumed
 'top_pipe_to_program' could be null (see line 2870)
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tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head:   e35184f321518acadb681928a016da21a9a20c13
commit: a689e8d1f80012f90384ebac9dcfac4201f9f77e drm/amd/display: check top_pipe_to_program pointer
config: mips-randconfig-m031-20221018
compiler: mips64el-linux-gcc (GCC) 12.1.0

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <dan.carpenter@oracle.com>

New smatch warnings:
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:3047 commit_planes_for_stream() error: we previously assumed 'top_pipe_to_program' could be null (see line 2870)

Old smatch warnings:
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:883 dc_construct_ctx() warn: possible memory leak of 'dc_ctx'
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:2285 det_surface_update() warn: variable dereferenced before check 'u->surface' (see line 2252)
drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:3058 commit_planes_for_stream() warn: variable dereferenced before check 'stream' (see line 2869)

vim +/top_pipe_to_program +3047 drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c

482812d56698ef Wesley Chalmers       2021-03-12  2868  
71b81f1275e0b5 Wenjing Liu           2020-01-22  2869  	if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
a689e8d1f80012 Yang Li               2021-11-15 @2870  		if (top_pipe_to_program &&
a689e8d1f80012 Yang Li               2021-11-15  2871  			top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {

Check for NULL

cfafe238b58596 Dan Carpenter         2020-07-14  2872  			if (should_use_dmub_lock(stream->link)) {
dc6e2448558d68 Wyatt Wood            2020-05-27  2873  				union dmub_hw_lock_flags hw_locks = { 0 };
dc6e2448558d68 Wyatt Wood            2020-05-27  2874  				struct dmub_hw_lock_inst_flags inst_flags = { 0 };
dc6e2448558d68 Wyatt Wood            2020-05-27  2875  
dc6e2448558d68 Wyatt Wood            2020-05-27  2876  				hw_locks.bits.lock_dig = 1;
dc6e2448558d68 Wyatt Wood            2020-05-27  2877  				inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
dc6e2448558d68 Wyatt Wood            2020-05-27  2878  
dc6e2448558d68 Wyatt Wood            2020-05-27  2879  				dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
dc6e2448558d68 Wyatt Wood            2020-05-27  2880  							true,
dc6e2448558d68 Wyatt Wood            2020-05-27  2881  							&hw_locks,
dc6e2448558d68 Wyatt Wood            2020-05-27  2882  							&inst_flags);
dc6e2448558d68 Wyatt Wood            2020-05-27  2883  			} else
71b81f1275e0b5 Wenjing Liu           2020-01-22  2884  				top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable(
71b81f1275e0b5 Wenjing Liu           2020-01-22  2885  						top_pipe_to_program->stream_res.tg);
dc6e2448558d68 Wyatt Wood            2020-05-27  2886  		}
71b81f1275e0b5 Wenjing Liu           2020-01-22  2887  
f9ccaf6da03134 Roy Chan              2021-07-21  2888  	if (should_lock_all_pipes && dc->hwss.interdependent_update_lock)
009114f6df8415 Anthony Koo           2020-01-14  2889  		dc->hwss.interdependent_update_lock(dc, context, true);
009114f6df8415 Anthony Koo           2020-01-14  2890  	else
009114f6df8415 Anthony Koo           2020-01-14  2891  		/* Lock the top pipe while updating plane addrs, since freesync requires
009114f6df8415 Anthony Koo           2020-01-14  2892  		 *  plane addr update event triggers to be synchronized.
009114f6df8415 Anthony Koo           2020-01-14  2893  		 *  top_pipe_to_program is expected to never be NULL
009114f6df8415 Anthony Koo           2020-01-14  2894  		 */
009114f6df8415 Anthony Koo           2020-01-14  2895  		dc->hwss.pipe_control_lock(dc, top_pipe_to_program, true);
009114f6df8415 Anthony Koo           2020-01-14  2896  
1e7e86c43f38d2 Samson Tam            2018-05-01  2897  	// Stream updates
1e7e86c43f38d2 Samson Tam            2018-05-01  2898  	if (stream_update)
1e7e86c43f38d2 Samson Tam            2018-05-01  2899  		commit_planes_do_stream_update(dc, stream, stream_update, update_type, context);
1e7e86c43f38d2 Samson Tam            2018-05-01  2900  
671a6246e0d365 Yongqiang Sun         2017-09-22  2901  	if (surface_count == 0) {
671a6246e0d365 Yongqiang Sun         2017-09-22  2902  		/*
671a6246e0d365 Yongqiang Sun         2017-09-22  2903  		 * In case of turning off screen, no need to program front end a second time.
1e7e86c43f38d2 Samson Tam            2018-05-01  2904  		 * just return after program blank.
671a6246e0d365 Yongqiang Sun         2017-09-22  2905  		 */
b6e881c947417e Dmytro Laktyushkin    2019-09-13  2906  		if (dc->hwss.apply_ctx_for_surface)
1e7e86c43f38d2 Samson Tam            2018-05-01  2907  			dc->hwss.apply_ctx_for_surface(dc, stream, 0, context);
b6e881c947417e Dmytro Laktyushkin    2019-09-13  2908  		if (dc->hwss.program_front_end_for_ctx)
b6e881c947417e Dmytro Laktyushkin    2019-09-13  2909  			dc->hwss.program_front_end_for_ctx(dc, context);
b6e881c947417e Dmytro Laktyushkin    2019-09-13  2910  
f9ccaf6da03134 Roy Chan              2021-07-21  2911  		if (should_lock_all_pipes && dc->hwss.interdependent_update_lock)
009114f6df8415 Anthony Koo           2020-01-14  2912  			dc->hwss.interdependent_update_lock(dc, context, false);
009114f6df8415 Anthony Koo           2020-01-14  2913  		else
009114f6df8415 Anthony Koo           2020-01-14  2914  			dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
bbf5f6c3f83bed Anthony Koo           2020-01-14  2915  		dc->hwss.post_unlock_program_front_end(dc, context);
671a6246e0d365 Yongqiang Sun         2017-09-22  2916  		return;
671a6246e0d365 Yongqiang Sun         2017-09-22  2917  	}
4562236b3bc0a2 Harry Wentland        2017-09-12  2918  
6fbefb84a98ecc Harry Wentland        2019-02-22  2919  	if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
6fbefb84a98ecc Harry Wentland        2019-02-22  2920  		for (i = 0; i < surface_count; i++) {
6fbefb84a98ecc Harry Wentland        2019-02-22  2921  			struct dc_plane_state *plane_state = srf_updates[i].surface;
6fbefb84a98ecc Harry Wentland        2019-02-22  2922  			/*set logical flag for lock/unlock use*/
6fbefb84a98ecc Harry Wentland        2019-02-22  2923  			for (j = 0; j < dc->res_pool->pipe_count; j++) {
6fbefb84a98ecc Harry Wentland        2019-02-22  2924  				struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
6fbefb84a98ecc Harry Wentland        2019-02-22  2925  				if (!pipe_ctx->plane_state)
6fbefb84a98ecc Harry Wentland        2019-02-22  2926  					continue;
f9ccaf6da03134 Roy Chan              2021-07-21  2927  				if (should_update_pipe_for_plane(context, pipe_ctx, plane_state))
6fbefb84a98ecc Harry Wentland        2019-02-22  2928  					continue;
f9ccaf6da03134 Roy Chan              2021-07-21  2929  				pipe_ctx->plane_state->triplebuffer_flips = false;
6fbefb84a98ecc Harry Wentland        2019-02-22  2930  				if (update_type == UPDATE_TYPE_FAST &&
6fbefb84a98ecc Harry Wentland        2019-02-22  2931  					dc->hwss.program_triplebuffer != NULL &&
f9ccaf6da03134 Roy Chan              2021-07-21  2932  					!pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) {
6fbefb84a98ecc Harry Wentland        2019-02-22  2933  						/*triple buffer for VUpdate  only*/
f9ccaf6da03134 Roy Chan              2021-07-21  2934  						pipe_ctx->plane_state->triplebuffer_flips = true;
6fbefb84a98ecc Harry Wentland        2019-02-22  2935  				}
6fbefb84a98ecc Harry Wentland        2019-02-22  2936  			}
56d63782af9bbd Anthony Wang          2021-03-31  2937  			if (update_type == UPDATE_TYPE_FULL) {
56d63782af9bbd Anthony Wang          2021-03-31  2938  				/* force vsync flip when reconfiguring pipes to prevent underflow */
56d63782af9bbd Anthony Wang          2021-03-31  2939  				plane_state->flip_immediate = false;
56d63782af9bbd Anthony Wang          2021-03-31  2940  			}
6fbefb84a98ecc Harry Wentland        2019-02-22  2941  		}
6fbefb84a98ecc Harry Wentland        2019-02-22  2942  	}
6fbefb84a98ecc Harry Wentland        2019-02-22  2943  
1e7e86c43f38d2 Samson Tam            2018-05-01  2944  	// Update Type FULL, Surface updates
156590454259a1 Bhawanpreet Lakha     2017-08-23  2945  	for (j = 0; j < dc->res_pool->pipe_count; j++) {
f19d5f3520d67c Dmytro Laktyushkin    2017-06-13  2946  		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
3e9ad6164b98f8 Eric Yang             2017-08-03  2947  
e6c258cb4e6fbc Yongqiang Sun         2017-10-30  2948  		if (!pipe_ctx->top_pipe &&
285e30049708c4 Dmytro Laktyushkin    2019-08-06  2949  			!pipe_ctx->prev_odm_pipe &&
f9ccaf6da03134 Roy Chan              2021-07-21  2950  			should_update_pipe_for_stream(context, pipe_ctx, stream)) {
05133ac856d078 SivapiriyanKumarasamy 2018-01-04  2951  			struct dc_stream_status *stream_status = NULL;
05133ac856d078 SivapiriyanKumarasamy 2018-01-04  2952  
98e6436d3af5fe Anthony Koo           2018-08-21  2953  			if (!pipe_ctx->plane_state)
98e6436d3af5fe Anthony Koo           2018-08-21  2954  				continue;
98e6436d3af5fe Anthony Koo           2018-08-21  2955  
98e6436d3af5fe Anthony Koo           2018-08-21  2956  			/* Full fe update*/
98e6436d3af5fe Anthony Koo           2018-08-21  2957  			if (update_type == UPDATE_TYPE_FAST)
05133ac856d078 SivapiriyanKumarasamy 2018-01-04  2958  				continue;
05133ac856d078 SivapiriyanKumarasamy 2018-01-04  2959  
6fbefb84a98ecc Harry Wentland        2019-02-22  2960  			ASSERT(!pipe_ctx->plane_state->triplebuffer_flips);
6fbefb84a98ecc Harry Wentland        2019-02-22  2961  
091018a51c16ec Aric Cyr              2020-08-21  2962  			if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
6fbefb84a98ecc Harry Wentland        2019-02-22  2963  				/*turn off triple buffer for full update*/
6fbefb84a98ecc Harry Wentland        2019-02-22  2964  				dc->hwss.program_triplebuffer(
6fbefb84a98ecc Harry Wentland        2019-02-22  2965  					dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
6fbefb84a98ecc Harry Wentland        2019-02-22  2966  			}
05133ac856d078 SivapiriyanKumarasamy 2018-01-04  2967  			stream_status =
e6c258cb4e6fbc Yongqiang Sun         2017-10-30  2968  				stream_get_status(context, pipe_ctx->stream);
3e9ad6164b98f8 Eric Yang             2017-08-03  2969  
b6e881c947417e Dmytro Laktyushkin    2019-09-13  2970  			if (dc->hwss.apply_ctx_for_surface)
156590454259a1 Bhawanpreet Lakha     2017-08-23  2971  				dc->hwss.apply_ctx_for_surface(
156590454259a1 Bhawanpreet Lakha     2017-08-23  2972  					dc, pipe_ctx->stream, stream_status->plane_count, context);
3e9ad6164b98f8 Eric Yang             2017-08-03  2973  		}
f19d5f3520d67c Dmytro Laktyushkin    2017-06-13  2974  	}
b9fe5151052f9d Jaehyun Chung         2019-10-31  2975  	if (dc->hwss.program_front_end_for_ctx && update_type != UPDATE_TYPE_FAST) {
b6e881c947417e Dmytro Laktyushkin    2019-09-13  2976  		dc->hwss.program_front_end_for_ctx(dc, context);
a4cea11655fbc5 Jaehyun Chung         2019-11-07  2977  #ifdef CONFIG_DRM_AMD_DC_DCN
b9fe5151052f9d Jaehyun Chung         2019-10-31  2978  		if (dc->debug.validate_dml_output) {
b9fe5151052f9d Jaehyun Chung         2019-10-31  2979  			for (i = 0; i < dc->res_pool->pipe_count; i++) {
b9fe5151052f9d Jaehyun Chung         2019-10-31  2980  				struct pipe_ctx cur_pipe = context->res_ctx.pipe_ctx[i];
b9fe5151052f9d Jaehyun Chung         2019-10-31  2981  				if (cur_pipe.stream == NULL)
b9fe5151052f9d Jaehyun Chung         2019-10-31  2982  					continue;
b9fe5151052f9d Jaehyun Chung         2019-10-31  2983  
b9fe5151052f9d Jaehyun Chung         2019-10-31  2984  				cur_pipe.plane_res.hubp->funcs->validate_dml_output(
b9fe5151052f9d Jaehyun Chung         2019-10-31  2985  						cur_pipe.plane_res.hubp, dc->ctx,
b9fe5151052f9d Jaehyun Chung         2019-10-31  2986  						&context->res_ctx.pipe_ctx[i].rq_regs,
b9fe5151052f9d Jaehyun Chung         2019-10-31  2987  						&context->res_ctx.pipe_ctx[i].dlg_regs,
b9fe5151052f9d Jaehyun Chung         2019-10-31  2988  						&context->res_ctx.pipe_ctx[i].ttu_regs);
b9fe5151052f9d Jaehyun Chung         2019-10-31  2989  			}
b9fe5151052f9d Jaehyun Chung         2019-10-31  2990  		}
b9fe5151052f9d Jaehyun Chung         2019-10-31  2991  #endif
b9fe5151052f9d Jaehyun Chung         2019-10-31  2992  	}
f19d5f3520d67c Dmytro Laktyushkin    2017-06-13  2993  
1e7e86c43f38d2 Samson Tam            2018-05-01  2994  	// Update Type FAST, Surface updates
1e7e86c43f38d2 Samson Tam            2018-05-01  2995  	if (update_type == UPDATE_TYPE_FAST) {
6fbefb84a98ecc Harry Wentland        2019-02-22  2996  		if (dc->hwss.set_flip_control_gsl)
00f02019990d90 Leon Elazar           2017-03-17  2997  			for (i = 0; i < surface_count; i++) {
3be5262e353b8a Harry Wentland        2017-07-27  2998  				struct dc_plane_state *plane_state = srf_updates[i].surface;
00f02019990d90 Leon Elazar           2017-03-17  2999  
156590454259a1 Bhawanpreet Lakha     2017-08-23  3000  				for (j = 0; j < dc->res_pool->pipe_count; j++) {
00f02019990d90 Leon Elazar           2017-03-17  3001  					struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
00f02019990d90 Leon Elazar           2017-03-17  3002  
f9ccaf6da03134 Roy Chan              2021-07-21  3003  					if (!should_update_pipe_for_stream(context, pipe_ctx, stream))
b8fce2c9d773e1 Yongqiang Sun         2017-11-07  3004  						continue;
b8fce2c9d773e1 Yongqiang Sun         2017-11-07  3005  
f9ccaf6da03134 Roy Chan              2021-07-21  3006  					if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))
00f02019990d90 Leon Elazar           2017-03-17  3007  						continue;
e72f0acd369d3d Tony Cheng            2017-01-19  3008  
6fbefb84a98ecc Harry Wentland        2019-02-22  3009  					// GSL has to be used for flip immediate
6fbefb84a98ecc Harry Wentland        2019-02-22  3010  					dc->hwss.set_flip_control_gsl(pipe_ctx,
f9ccaf6da03134 Roy Chan              2021-07-21  3011  							pipe_ctx->plane_state->flip_immediate);
6fbefb84a98ecc Harry Wentland        2019-02-22  3012  				}
6fbefb84a98ecc Harry Wentland        2019-02-22  3013  			}
980d6042c1dc0d Wyatt Wood            2021-01-19  3014  
6fbefb84a98ecc Harry Wentland        2019-02-22  3015  		/* Perform requested Updates */
6fbefb84a98ecc Harry Wentland        2019-02-22  3016  		for (i = 0; i < surface_count; i++) {
6fbefb84a98ecc Harry Wentland        2019-02-22  3017  			struct dc_plane_state *plane_state = srf_updates[i].surface;
6fbefb84a98ecc Harry Wentland        2019-02-22  3018  
6fbefb84a98ecc Harry Wentland        2019-02-22  3019  			for (j = 0; j < dc->res_pool->pipe_count; j++) {
6fbefb84a98ecc Harry Wentland        2019-02-22  3020  				struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
6fbefb84a98ecc Harry Wentland        2019-02-22  3021  
f9ccaf6da03134 Roy Chan              2021-07-21  3022  				if (!should_update_pipe_for_stream(context, pipe_ctx, stream))
6fbefb84a98ecc Harry Wentland        2019-02-22  3023  					continue;
6fbefb84a98ecc Harry Wentland        2019-02-22  3024  
f9ccaf6da03134 Roy Chan              2021-07-21  3025  				if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state))
6fbefb84a98ecc Harry Wentland        2019-02-22  3026  					continue;
f9ccaf6da03134 Roy Chan              2021-07-21  3027  
6fbefb84a98ecc Harry Wentland        2019-02-22  3028  				/*program triple buffer after lock based on flip type*/
091018a51c16ec Aric Cyr              2020-08-21  3029  				if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) {
6fbefb84a98ecc Harry Wentland        2019-02-22  3030  					/*only enable triplebuffer for  fast_update*/
6fbefb84a98ecc Harry Wentland        2019-02-22  3031  					dc->hwss.program_triplebuffer(
f9ccaf6da03134 Roy Chan              2021-07-21  3032  						dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips);
6fbefb84a98ecc Harry Wentland        2019-02-22  3033  				}
f9ccaf6da03134 Roy Chan              2021-07-21  3034  				if (pipe_ctx->plane_state->update_flags.bits.addr_update)
156590454259a1 Bhawanpreet Lakha     2017-08-23  3035  					dc->hwss.update_plane_addr(dc, pipe_ctx);
56ef6ed9faf35b Anthony Koo           2017-10-23  3036  			}
56ef6ed9faf35b Anthony Koo           2017-10-23  3037  		}
980d6042c1dc0d Wyatt Wood            2021-01-19  3038  
009114f6df8415 Anthony Koo           2020-01-14  3039  	}
56ef6ed9faf35b Anthony Koo           2017-10-23  3040  
f9ccaf6da03134 Roy Chan              2021-07-21  3041  	if (should_lock_all_pipes && dc->hwss.interdependent_update_lock)
009114f6df8415 Anthony Koo           2020-01-14  3042  		dc->hwss.interdependent_update_lock(dc, context, false);
009114f6df8415 Anthony Koo           2020-01-14  3043  	else
05133ac856d078 SivapiriyanKumarasamy 2018-01-04  3044  		dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false);
e63e2491ad9203 Eryk Brol             2019-04-23  3045  
71b81f1275e0b5 Wenjing Liu           2020-01-22  3046  	if ((update_type != UPDATE_TYPE_FAST) && stream->update_flags.bits.dsc_changed)
71b81f1275e0b5 Wenjing Liu           2020-01-22 @3047  		if (top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_enable) {

Unchecked dereference

71b81f1275e0b5 Wenjing Liu           2020-01-22  3048  			top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
71b81f1275e0b5 Wenjing Liu           2020-01-22  3049  					top_pipe_to_program->stream_res.tg,
71b81f1275e0b5 Wenjing Liu           2020-01-22  3050  					CRTC_STATE_VACTIVE);
71b81f1275e0b5 Wenjing Liu           2020-01-22  3051  			top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
71b81f1275e0b5 Wenjing Liu           2020-01-22  3052  					top_pipe_to_program->stream_res.tg,
71b81f1275e0b5 Wenjing Liu           2020-01-22  3053  					CRTC_STATE_VBLANK);
71b81f1275e0b5 Wenjing Liu           2020-01-22  3054  			top_pipe_to_program->stream_res.tg->funcs->wait_for_state(
71b81f1275e0b5 Wenjing Liu           2020-01-22  3055  					top_pipe_to_program->stream_res.tg,
71b81f1275e0b5 Wenjing Liu           2020-01-22  3056  					CRTC_STATE_VACTIVE);
dc6e2448558d68 Wyatt Wood            2020-05-27  3057  
dc6e2448558d68 Wyatt Wood            2020-05-27  3058  			if (stream && should_use_dmub_lock(stream->link)) {
dc6e2448558d68 Wyatt Wood            2020-05-27  3059  				union dmub_hw_lock_flags hw_locks = { 0 };
dc6e2448558d68 Wyatt Wood            2020-05-27  3060  				struct dmub_hw_lock_inst_flags inst_flags = { 0 };
dc6e2448558d68 Wyatt Wood            2020-05-27  3061  
dc6e2448558d68 Wyatt Wood            2020-05-27  3062  				hw_locks.bits.lock_dig = 1;
dc6e2448558d68 Wyatt Wood            2020-05-27  3063  				inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
dc6e2448558d68 Wyatt Wood            2020-05-27  3064  
dc6e2448558d68 Wyatt Wood            2020-05-27  3065  				dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
dc6e2448558d68 Wyatt Wood            2020-05-27  3066  							false,
dc6e2448558d68 Wyatt Wood            2020-05-27  3067  							&hw_locks,
dc6e2448558d68 Wyatt Wood            2020-05-27  3068  							&inst_flags);
dc6e2448558d68 Wyatt Wood            2020-05-27  3069  			} else
71b81f1275e0b5 Wenjing Liu           2020-01-22  3070  				top_pipe_to_program->stream_res.tg->funcs->lock_doublebuffer_disable(
71b81f1275e0b5 Wenjing Liu           2020-01-22  3071  					top_pipe_to_program->stream_res.tg);
71b81f1275e0b5 Wenjing Liu           2020-01-22  3072  		}
71b81f1275e0b5 Wenjing Liu           2020-01-22  3073  
bbf5f6c3f83bed Anthony Koo           2020-01-14  3074  	if (update_type != UPDATE_TYPE_FAST)
bbf5f6c3f83bed Anthony Koo           2020-01-14  3075  		dc->hwss.post_unlock_program_front_end(dc, context);
bbf5f6c3f83bed Anthony Koo           2020-01-14  3076  
4fd334122399a1 Aric Cyr              2019-05-16  3077  	// Fire manual trigger only when bottom plane is flipped
4fd334122399a1 Aric Cyr              2019-05-16  3078  	for (j = 0; j < dc->res_pool->pipe_count; j++) {
4fd334122399a1 Aric Cyr              2019-05-16  3079  		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
e63e2491ad9203 Eryk Brol             2019-04-23  3080  
148493a81e3b60 Robin Singh           2021-03-09  3081  		if (!pipe_ctx->plane_state)
148493a81e3b60 Robin Singh           2021-03-09  3082  			continue;
148493a81e3b60 Robin Singh           2021-03-09  3083  
35a4644c935ee8 Aric Cyr              2020-10-08  3084  		if (pipe_ctx->bottom_pipe || pipe_ctx->next_odm_pipe ||
f9ccaf6da03134 Roy Chan              2021-07-21  3085  				!pipe_ctx->stream || !should_update_pipe_for_stream(context, pipe_ctx, stream) ||
41ef8fbbef8e21 Aric Cyr              2021-03-17  3086  				!pipe_ctx->plane_state->update_flags.bits.addr_update ||
41ef8fbbef8e21 Aric Cyr              2021-03-17  3087  				pipe_ctx->plane_state->skip_manual_trigger)
e63e2491ad9203 Eryk Brol             2019-04-23  3088  			continue;
e63e2491ad9203 Eryk Brol             2019-04-23  3089  
e63e2491ad9203 Eryk Brol             2019-04-23  3090  		if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger)
e63e2491ad9203 Eryk Brol             2019-04-23  3091  			pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg);
e63e2491ad9203 Eryk Brol             2019-04-23  3092  	}
4562236b3bc0a2 Harry Wentland        2017-09-12  3093  }

-- 
0-DAY CI Kernel Test Service
https://01.org/lkp