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From:   Niklas Cassel <Niklas.Cassel@wdc.com>
To:     John Garry <john.garry@huawei.com>
CC:     Damien Le Moal <damien.lemoal@opensource.wdc.com>,
        "jejb@linux.ibm.com" <jejb@linux.ibm.com>,
        "martin.petersen@oracle.com" <martin.petersen@oracle.com>,
        "jinpu.wang@cloud.ionos.com" <jinpu.wang@cloud.ionos.com>,
        "linux-scsi@vger.kernel.org" <linux-scsi@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Linuxarm <linuxarm@huawei.com>,
        yangxingui <yangxingui@huawei.com>,
        yanaijie <yanaijie@huawei.com>
Subject: Re: [PATCH v5 0/7] libsas and drivers: NCQ error handling
Thread-Topic: [PATCH v5 0/7] libsas and drivers: NCQ error handling
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Date:   Mon, 24 Oct 2022 13:10:06 +0000
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On Mon, Oct 24, 2022 at 01:44:56PM +0100, John Garry wrote:
> Hi Niklas,
>=20
> >=20
> > For the record, I tested the pm80xx driver on a HoneyComb LX2 board
> > (an arm64 board using ACPI).
> >=20
> > I tried v6.1-rc1 both with and without your series in $subject.
> >=20
> > I couldn't see any issues.
>=20
> ok, thanks for the effort.
>=20
> >=20
> >=20
> > What I tried:
> > -Running fio:
> > fio --name=3Dtest --filename=3D/dev/sdc --ioengine=3Dio_uring --rw=3Dra=
ndrw --direct=3D1 --iodepth=3D32 --bs=3D1M
> > on three different HDDs simultaneously for 15+ minutes,
> > without any errors in fio or dmesg.
> >=20
> > -Creating and mounting a btrfs volume, doing a huge dd to the filesyste=
m
> > without issues.
> >=20
> > -sg_sat_read_gplog -d --log=3D0x10 /dev/sda
> > which successfully returned the log.
> >=20
> >=20
> > It is worth mentioning that this arm64 board has reserved memory region=
s,
> > but does not yet have a firmware that supplies a IORT RMR (reserved mem=
ory
> > regions) revision E.d node, which means that in order to get this board=
 to
> > boot successfully, we need to supply:
> > "arm-smmu.disable_bypass=3D0 iommu.passthrough=3D1"
> > on the kernel command line.
>=20
> hmmm... that's interesting. I can try again with the IOMMU turned off, bu=
t,
> as I recall, it did not make a difference before. I think that requiring
> reserved memory regions would totally bust the driver (if not present) wi=
th
> IOMMU enabled. As I recall, sas 3008 card would not work without RMR for =
us.

At least on the HoneyComb LX2,
running with "arm-smmu.disable_bypass=3D0 iommu.passthrough=3D1" gives a wo=
rking
system (and working pm80xx).

The ACPI IOMMU code that parses the ACPI IORT RMR revision E.d node
was first included in kernel v6.0:
https://lore.kernel.org/linux-iommu/20220615101044.1972-1-shameerali.koloth=
um.thodi@huawei.com/

However, the HoneyComb edk2-platforms code has not yet been updated to add
a ACPI IORT RMR revision E.d node.

Considering that it works with "arm-smmu.disable_bypass=3D0 iommu.passthrou=
gh=3D1",
I assume that the ACPI IORT RMR node basically just defines a number of
memory regions which the IOMMU should treat as "bypass", while all other
memory has to be re-mapped via the IOMMU as per usual.


Kind regards,
Niklas=