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References: <20221024102307.33722-1-angelogioacchino.delregno@collabora.com> <20221024102307.33722-2-angelogioacchino.delregno@collabora.com>
In-Reply-To: <20221024102307.33722-2-angelogioacchino.delregno@collabora.com>
From:   Chen-Yu Tsai <wenst@chromium.org>
Date:   Mon, 24 Oct 2022 14:57:09 -0700
Message-ID: <CAGXv+5HnJgmoX=8596OJZki_0qDaipP+cbbTWpkVxuOkErSBdA@mail.gmail.com>
Subject: Re: [PATCH 01/10] clk: mediatek: clk-mtk: Allow specifying flags on
 mtk_fixed_factor clocks
To:     AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@collabora.com>
Cc:     sboyd@kernel.org, mturquette@baylibre.com, matthias.bgg@gmail.com,
        miles.chen@mediatek.com, nfraprado@collabora.com,
        rex-bc.chen@mediatek.com, chun-jie.chen@mediatek.com,
        jose.exposito89@gmail.com, yangyingliang@huawei.com,
        msp@baylibre.com, linux-clk@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org,
        linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org
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On Mon, Oct 24, 2022 at 3:23 AM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> Before this change, every mtk_fixed_factor clock forced clock flags to
> CLK_SET_RATE_PARENT: while this is harmless in some cases, it may not
> be desired in some others, especially when performing clock muxing on
> a clock having multiple parents of which one is a dedicated PLL and the
> others are not.
>
> This is especially seen on the GPU clocks on some SoCs, where we are
> muxing between multiple parents: a fixed clock (crystal), a programmable
> GPU PLL and one or more dividers for the MAINPLL, used for a number of
> devices; it happens that when a rate change is called for the GPU, the
> clock framework will try to satisfy the rate request by using one of the
> MAINPLL dividers, which have CLK_SET_RATE_PARENT and will set the rate
> on MAINPLL itself - overclocking or underclocking many devices in the
> system - and making it to lock up.
>
> Logically, it should be harmless (and would only reduce possible bugs)
> to change all of the univpll and mainpll related fixed factor clocks
> to not declare the CLK_SET_RATE_PARENT by default but, on some SoCs,
> this is also used for dividers of other PLLs for which a rate change
> based on the divider may be desired, hence introduce a new FACTOR_FLAGS()
> macro to use custom flags (or none) on selected fixed factor clocks.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>