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Mon, 24 Oct 2022 19:21:53 -0700 Received: from [10.110.48.28] (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Mon, 24 Oct 2022 19:21:52 -0700 Message-ID: Date: Mon, 24 Oct 2022 19:21:52 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.0 Subject: Re: [RFC PATCH 0/3] new subsystem for compute accelerator devices Content-Language: en-US To: Oded Gabbay , Thomas Zimmermann CC: David Airlie , Daniel Vetter , "Arnd Bergmann" , Greg Kroah-Hartman , , , "Jason Gunthorpe" , Alex Deucher , "Maarten Lankhorst" , Maxime Ripard , Yuji Ishikawa , Jiho Chu , Daniel Stone , Tvrtko Ursulin , Jeffrey Hugo , Christoph Hellwig , Kevin Hilman , Jagan Teki , Jacek Lawrynowicz , Maciej Kwapulinski References: <20221022214622.18042-1-ogabbay@kernel.org> From: John Hubbard In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT023:EE_|CY8PR12MB7364:EE_ X-MS-Office365-Filtering-Correlation-Id: c649fd85-7601-4774-bf02-08dab62fafe5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Oct 2022 02:21:55.6196 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c649fd85-7601-4774-bf02-08dab62fafe5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT023.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7364 X-Spam-Status: No, score=-1.6 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, NICE_REPLY_A,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, SPF_NONE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 10/24/22 05:43, Oded Gabbay wrote: Hi Oded, The patches make sense to me. I'm still just reading through and looking for minor issues, but at a high level it seems to match what the LPC discussions pointed to. >> What's your opinion on the long-term prospect of DRM vs accel? I assume >> that over time, DRM helpers will move into accel and some DRM drivers >> will start depending on accel? > I don't think that is what I had in mind. > What I had in mind is that accel helpers are only relevant for accel > drivers, and any code that might also be relevant for DRM drivers will > be placed in DRM core code. e.g. GEM enhancements, RAS netlink Yes. That is how I understood it ("it" being both the LPC discussions, and this patchset) as well: * accel-only code goes in drivers/accel, thus allowing for smaller, simpler drivers (as compared to full drm) for that case. * graphics and display code still goes in drivers/gpu/drm, because it is much too hard to rename or move that directory. * code common to both also goes in drivers/gpu/drm. Looking ahead a bit more: For full-featured GPUs that do both Graphics and Compute, I expect that a *lot* of the code will end up in drivers/gpu/drm. Because so much of setting up for Compute is also really just setting up for Graphics--that's how it evolved, after all! And as things are structured now, it looks like those full featured GPU stacks will also need an aux bus (which I only just now learned about, but it looks quite helpful here). And also, user space will need to open both /dev/dri/* and /dev/accel/* nodes, if it needs access to anything live objects that drivers/accel owns. thanks, -- John Hubbard NVIDIA