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Date:   Tue, 25 Oct 2022 08:44:10 +0200
From:   Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
To:     Paul Cercueil <paul@crapouillou.net>
Cc:     Thierry Reding <thierry.reding@gmail.com>, od@opendingux.net,
        linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-mips@vger.kernel.org, stable@vger.kernel.org
Subject: Re: [PATCH 2/5] pwm: jz4740: Fix pin level of disabled TCU2
 channels, part 2
Message-ID: <20221025064410.brrx5faa4jtwo67b@pengutronix.de>
References: <20221024205213.327001-1-paul@crapouillou.net>
 <20221024205213.327001-3-paul@crapouillou.net>
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On Mon, Oct 24, 2022 at 09:52:10PM +0100, Paul Cercueil wrote:
> After commit a020f22a4ff5 ("pwm: jz4740: Make PWM start with the active p=
art"),
> the trick to set duty > period to properly shut down TCU2 channels did
> not work anymore, because of the polarity inversion.
>=20
> Address this issue by restoring the proper polarity before disabling the
> channels.
>=20
> Fixes: a020f22a4ff5 ("pwm: jz4740: Make PWM start with the active part")
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> Cc: stable@vger.kernel.org
> ---
>  drivers/pwm/pwm-jz4740.c | 62 ++++++++++++++++++++++++++--------------
>  1 file changed, 40 insertions(+), 22 deletions(-)
>=20
> diff --git a/drivers/pwm/pwm-jz4740.c b/drivers/pwm/pwm-jz4740.c
> index 228eb104bf1e..65462a0052af 100644
> --- a/drivers/pwm/pwm-jz4740.c
> +++ b/drivers/pwm/pwm-jz4740.c
> @@ -97,6 +97,19 @@ static int jz4740_pwm_enable(struct pwm_chip *chip, st=
ruct pwm_device *pwm)
>  	return 0;
>  }
> =20
> +static void jz4740_pwm_set_polarity(struct jz4740_pwm_chip *jz,
> +				    unsigned int hwpwm,
> +				    enum pwm_polarity polarity)
> +{
> +	unsigned int value =3D 0;
> +
> +	if (polarity =3D=3D PWM_POLARITY_INVERSED)
> +		value =3D TCU_TCSR_PWM_INITL_HIGH;
> +
> +	regmap_update_bits(jz->map, TCU_REG_TCSRc(hwpwm),
> +			   TCU_TCSR_PWM_INITL_HIGH, value);
> +}
> +
>  static void jz4740_pwm_disable(struct pwm_chip *chip, struct pwm_device =
*pwm)
>  {
>  	struct jz4740_pwm_chip *jz =3D to_jz4740(chip);
> @@ -130,6 +143,7 @@ static int jz4740_pwm_apply(struct pwm_chip *chip, st=
ruct pwm_device *pwm,
>  	unsigned long long tmp =3D 0xffffull * NSEC_PER_SEC;
>  	struct clk *clk =3D pwm_get_chip_data(pwm);
>  	unsigned long period, duty;
> +	enum pwm_polarity polarity;
>  	long rate;
>  	int err;
> =20
> @@ -169,6 +183,9 @@ static int jz4740_pwm_apply(struct pwm_chip *chip, st=
ruct pwm_device *pwm,
>  	if (duty >=3D period)
>  		duty =3D period - 1;
> =20
> +	/* Restore regular polarity before disabling the channel. */
> +	jz4740_pwm_set_polarity(jz4740, pwm->hwpwm, state->polarity);
> +

Does this introduce a glitch?

>  	jz4740_pwm_disable(chip, pwm);
> =20
>  	err =3D clk_set_rate(clk, rate);
> @@ -190,29 +207,30 @@ static int jz4740_pwm_apply(struct pwm_chip *chip, =
struct pwm_device *pwm,
>  	regmap_update_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm),
>  			   TCU_TCSR_PWM_SD, TCU_TCSR_PWM_SD);
> =20
> -	/*
> -	 * Set polarity.
> -	 *
> -	 * The PWM starts in inactive state until the internal timer reaches the
> -	 * duty value, then becomes active until the timer reaches the period
> -	 * value. In theory, we should then use (period - duty) as the real duty
> -	 * value, as a high duty value would otherwise result in the PWM pin
> -	 * being inactive most of the time.
> -	 *
> -	 * Here, we don't do that, and instead invert the polarity of the PWM
> -	 * when it is active. This trick makes the PWM start with its active
> -	 * state instead of its inactive state.
> -	 */
> -	if ((state->polarity =3D=3D PWM_POLARITY_NORMAL) ^ state->enabled)
> -		regmap_update_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm),
> -				   TCU_TCSR_PWM_INITL_HIGH, 0);
> -	else
> -		regmap_update_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm),
> -				   TCU_TCSR_PWM_INITL_HIGH,
> -				   TCU_TCSR_PWM_INITL_HIGH);
> -
> -	if (state->enabled)
> +	if (state->enabled) {
> +		/*
> +		 * Set polarity.
> +		 *
> +		 * The PWM starts in inactive state until the internal timer
> +		 * reaches the duty value, then becomes active until the timer
> +		 * reaches the period value. In theory, we should then use
> +		 * (period - duty) as the real duty value, as a high duty value
> +		 * would otherwise result in the PWM pin being inactive most of
> +		 * the time.
> +		 *
> +		 * Here, we don't do that, and instead invert the polarity of
> +		 * the PWM when it is active. This trick makes the PWM start
> +		 * with its active state instead of its inactive state.
> +		 */
> +		if (state->polarity =3D=3D PWM_POLARITY_NORMAL)
> +			polarity =3D PWM_POLARITY_INVERSED;
> +		else
> +			polarity =3D PWM_POLARITY_NORMAL;
> +
> +		jz4740_pwm_set_polarity(jz4740, pwm->hwpwm, polarity);
> +
>  		jz4740_pwm_enable(chip, pwm);
> +	}

Note that for disabled PWMs there is no official guaranty about the pin
state. So it would be ok (but admittedly not great) to simplify the
driver and accept that the pinstate is active while the PWM is off.
IMHO this is also better than a glitch.

If a consumer wants the PWM to be in its inactive state, they should
not disable it.

Best regards
Uwe

--=20
Pengutronix e.K.                           | Uwe Kleine-K=F6nig            |
Industrial Linux Solutions                 | https://www.pengutronix.de/ |

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