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[209.85.128.174]) by smtp.gmail.com with ESMTPSA id g3-20020ac87d03000000b00342f8984348sm1570874qtb.87.2022.10.25.05.37.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 25 Oct 2022 05:37:19 -0700 (PDT) Received: by mail-yw1-f174.google.com with SMTP id 00721157ae682-369426664f9so111664067b3.12; Tue, 25 Oct 2022 05:37:19 -0700 (PDT) X-Received: by 2002:a0d:de43:0:b0:349:31bd:e8d5 with SMTP id h64-20020a0dde43000000b0034931bde8d5mr32925900ywe.283.1666701438736; Tue, 25 Oct 2022 05:37:18 -0700 (PDT) MIME-Version: 1.0 References: <20221017091201.199457-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20221017091201.199457-3-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20221017091201.199457-3-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Geert Uytterhoeven Date: Tue, 25 Oct 2022 14:37:07 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [RFC RESEND PATCH 2/2] arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts To: Prabhakar Cc: Magnus Damm , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Olof Johansson , soc@kernel.org, linux-arm-kernel@lists.infradead.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , linux-riscv@lists.infradead.org, Conor Dooley , Samuel Holland , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-1.6 required=5.0 tests=BAYES_00, FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Prabhakar, On Mon, Oct 17, 2022 at 11:12 AM Prabhakar wrote: > From: Lad Prabhakar > > Move RZ/G2UL SoC specific parts to r9a07g043u.dtsi so that r9a07g043.dtsi > can be shared with RZ/Five (RISC-V SoC). > > Below are the changes due to which SoC specific parts are moved to > r9a07g043u.dtsi: > - RZ/G2UL has Cortex-A55 (ARM64) whereas the RZ/Five has AX45MP (RISC-V) > - RZ/G2UL has GICv3 as interrupt controller whereas the RZ/Five has PLIC > - RZ/G2UL has interrupts for SYSC block whereas interrupts are missing > for SYSC block on RZ/Five > > Signed-off-by: Lad Prabhakar Thanks for your patch! This assumes the operating points tables are the same for both variants? I guess that's OK. Overall, LGTM. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds