Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
MIME-Version: 1.0
References: <20221022214622.18042-1-ogabbay@kernel.org> <af4c71cb-be60-e354-ca4f-23e834aca6e1@suse.de>
 <CAFCwf12HDZvsr1TrRFQH9Vi26S-Xf9ULgxtBazme90Sj5AzhQQ@mail.gmail.com>
 <c22bd93e-8bd2-6865-711a-37aeadbca7f9@nvidia.com> <CAPM=9tyEqzQ09WcRtE1Zd3XjOaR9a2ms-vL-O5x2ong7iPF=4w@mail.gmail.com>
 <Y1fFRIxRq+enLWyd@nvidia.com> <CADnq5_PH3xR_nnN2wQ2NjydUoT+X0z_9OvHtaabwcPbwP-o+9A@mail.gmail.com>
 <Y1fz89kib4zVuqn5@nvidia.com>
In-Reply-To: <Y1fz89kib4zVuqn5@nvidia.com>
From:   Alex Deucher <alexdeucher@gmail.com>
Date:   Tue, 25 Oct 2022 10:43:01 -0400
Message-ID: <CADnq5_OuVWTmgRZsyF50VdJg0AfSS7_3cN2UCWrBDayXcPUkSQ@mail.gmail.com>
Subject: Re: [RFC PATCH 0/3] new subsystem for compute accelerator devices
To:     Jason Gunthorpe <jgg@nvidia.com>
Cc:     Dave Airlie <airlied@gmail.com>,
        Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>,
        Jiho Chu <jiho.chu@samsung.com>,
        Jeffrey Hugo <quic_jhugo@quicinc.com>,
        Thomas Zimmermann <tzimmermann@suse.de>,
        Arnd Bergmann <arnd@arndb.de>,
        John Hubbard <jhubbard@nvidia.com>,
        Oded Gabbay <ogabbay@kernel.org>, linux-kernel@vger.kernel.org,
        dri-devel@lists.freedesktop.org,
        Christoph Hellwig <hch@infradead.org>,
        Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        Alex Deucher <alexander.deucher@amd.com>,
        Yuji Ishikawa <yuji2.ishikawa@toshiba.co.jp>,
        Kevin Hilman <khilman@baylibre.com>,
        Maciej Kwapulinski <maciej.kwapulinski@linux.intel.com>,
        Jagan Teki <jagan@amarulasolutions.com>
Content-Type: text/plain; charset="UTF-8"
Precedence: bulk

On Tue, Oct 25, 2022 at 10:34 AM Jason Gunthorpe <jgg@nvidia.com> wrote:
>
> On Tue, Oct 25, 2022 at 10:21:34AM -0400, Alex Deucher wrote:
>
> > E.g., the kfd node provides platform level compute
> > topology information; e.g., the NUMA details for connected GPUs and
> > CPUs, non-GPU compute node information, cache level topologies, etc.
>
> See, this is exactly what I'm talking about. What on earth does any of
> this have to do with DRM?

At least for the GPU information it seems relevant.  What value are
acceleration device cache topologies outside of the subsytsem that
uses them?

>
> We alread have places in the kernel that own and expose these kinds of
> information, drivers need to use them. Not re-invent them.

I don't disagree, but I'm not sure where the best place for these
should be.  Probably a lack of knowledge of where this should actually
live and indifference from the maintainers of those areas since this
use case doesn't match existing ones.

Alex