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Date:   Tue, 25 Oct 2022 17:16:44 +0200
From:   Paul Kocialkowski <paul.kocialkowski@bootlin.com>
To:     Jernej Skrabec <jernej.skrabec@gmail.com>
Cc:     mripard@kernel.org, mchehab@kernel.org, gregkh@linuxfoundation.org,
        wens@csie.org, samuel@sholland.org, hverkuil-cisco@xs4all.nl,
        linux-media@vger.kernel.org, linux-staging@lists.linux.dev,
        linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH 05/11] media: cedrus: Filter controls based on capability
Message-ID: <Y1f93E4HvTVr2DuC@aptenodytes>
References: <20221024201515.34129-1-jernej.skrabec@gmail.com>
 <20221024201515.34129-6-jernej.skrabec@gmail.com>
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Hi,

On Mon 24 Oct 22, 22:15, Jernej Skrabec wrote:
> Because not all Cedrus variants supports all codecs, controls should be
> registered only if codec related to individual control is supported by
> Cedrus.
>=20
> Replace codec enum, which is not used at all, with capabilities flags
> and register control only if capabilities are met.
>=20
> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Acked-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>

Cheers,

Paul

> ---
>  drivers/staging/media/sunxi/cedrus/cedrus.c | 45 +++++++++++----------
>  drivers/staging/media/sunxi/cedrus/cedrus.h |  2 +-
>  2 files changed, 25 insertions(+), 22 deletions(-)
>=20
> diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/stagin=
g/media/sunxi/cedrus/cedrus.c
> index 2f284a58d787..023566b02dc5 100644
> --- a/drivers/staging/media/sunxi/cedrus/cedrus.c
> +++ b/drivers/staging/media/sunxi/cedrus/cedrus.c
> @@ -77,56 +77,56 @@ static const struct cedrus_control cedrus_controls[] =
=3D {
>  		.cfg =3D {
>  			.id	=3D V4L2_CID_STATELESS_MPEG2_SEQUENCE,
>  		},
> -		.codec		=3D CEDRUS_CODEC_MPEG2,
> +		.capabilities	=3D CEDRUS_CAPABILITY_MPEG2_DEC,
>  	},
>  	{
>  		.cfg =3D {
>  			.id	=3D V4L2_CID_STATELESS_MPEG2_PICTURE,
>  		},
> -		.codec		=3D CEDRUS_CODEC_MPEG2,
> +		.capabilities	=3D CEDRUS_CAPABILITY_MPEG2_DEC,
>  	},
>  	{
>  		.cfg =3D {
>  			.id	=3D V4L2_CID_STATELESS_MPEG2_QUANTISATION,
>  		},
> -		.codec		=3D CEDRUS_CODEC_MPEG2,
> +		.capabilities	=3D CEDRUS_CAPABILITY_MPEG2_DEC,
>  	},
>  	{
>  		.cfg =3D {
>  			.id	=3D V4L2_CID_STATELESS_H264_DECODE_PARAMS,
>  		},
> -		.codec		=3D CEDRUS_CODEC_H264,
> +		.capabilities	=3D CEDRUS_CAPABILITY_H264_DEC,
>  	},
>  	{
>  		.cfg =3D {
>  			.id	=3D V4L2_CID_STATELESS_H264_SLICE_PARAMS,
>  		},
> -		.codec		=3D CEDRUS_CODEC_H264,
> +		.capabilities	=3D CEDRUS_CAPABILITY_H264_DEC,
>  	},
>  	{
>  		.cfg =3D {
>  			.id	=3D V4L2_CID_STATELESS_H264_SPS,
>  			.ops	=3D &cedrus_ctrl_ops,
>  		},
> -		.codec		=3D CEDRUS_CODEC_H264,
> +		.capabilities	=3D CEDRUS_CAPABILITY_H264_DEC,
>  	},
>  	{
>  		.cfg =3D {
>  			.id	=3D V4L2_CID_STATELESS_H264_PPS,
>  		},
> -		.codec		=3D CEDRUS_CODEC_H264,
> +		.capabilities	=3D CEDRUS_CAPABILITY_H264_DEC,
>  	},
>  	{
>  		.cfg =3D {
>  			.id	=3D V4L2_CID_STATELESS_H264_SCALING_MATRIX,
>  		},
> -		.codec		=3D CEDRUS_CODEC_H264,
> +		.capabilities	=3D CEDRUS_CAPABILITY_H264_DEC,
>  	},
>  	{
>  		.cfg =3D {
>  			.id	=3D V4L2_CID_STATELESS_H264_PRED_WEIGHTS,
>  		},
> -		.codec		=3D CEDRUS_CODEC_H264,
> +		.capabilities	=3D CEDRUS_CAPABILITY_H264_DEC,
>  	},
>  	{
>  		.cfg =3D {
> @@ -134,7 +134,7 @@ static const struct cedrus_control cedrus_controls[] =
=3D {
>  			.max	=3D V4L2_STATELESS_H264_DECODE_MODE_SLICE_BASED,
>  			.def	=3D V4L2_STATELESS_H264_DECODE_MODE_SLICE_BASED,
>  		},
> -		.codec		=3D CEDRUS_CODEC_H264,
> +		.capabilities	=3D CEDRUS_CAPABILITY_H264_DEC,
>  	},
>  	{
>  		.cfg =3D {
> @@ -142,7 +142,7 @@ static const struct cedrus_control cedrus_controls[] =
=3D {
>  			.max	=3D V4L2_STATELESS_H264_START_CODE_NONE,
>  			.def	=3D V4L2_STATELESS_H264_START_CODE_NONE,
>  		},
> -		.codec		=3D CEDRUS_CODEC_H264,
> +		.capabilities	=3D CEDRUS_CAPABILITY_H264_DEC,
>  	},
>  	/*
>  	 * We only expose supported profiles information,
> @@ -160,20 +160,20 @@ static const struct cedrus_control cedrus_controls[=
] =3D {
>  			.menu_skip_mask =3D
>  				BIT(V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED),
>  		},
> -		.codec		=3D CEDRUS_CODEC_H264,
> +		.capabilities	=3D CEDRUS_CAPABILITY_H264_DEC,
>  	},
>  	{
>  		.cfg =3D {
>  			.id	=3D V4L2_CID_STATELESS_HEVC_SPS,
>  			.ops	=3D &cedrus_ctrl_ops,
>  		},
> -		.codec		=3D CEDRUS_CODEC_H265,
> +		.capabilities	=3D CEDRUS_CAPABILITY_H265_DEC,
>  	},
>  	{
>  		.cfg =3D {
>  			.id	=3D V4L2_CID_STATELESS_HEVC_PPS,
>  		},
> -		.codec		=3D CEDRUS_CODEC_H265,
> +		.capabilities	=3D CEDRUS_CAPABILITY_H265_DEC,
>  	},
>  	{
>  		.cfg =3D {
> @@ -181,13 +181,13 @@ static const struct cedrus_control cedrus_controls[=
] =3D {
>  			/* The driver can only handle 1 entry per slice for now */
>  			.dims   =3D { 1 },
>  		},
> -		.codec		=3D CEDRUS_CODEC_H265,
> +		.capabilities	=3D CEDRUS_CAPABILITY_H265_DEC,
>  	},
>  	{
>  		.cfg =3D {
>  			.id	=3D V4L2_CID_STATELESS_HEVC_SCALING_MATRIX,
>  		},
> -		.codec		=3D CEDRUS_CODEC_H265,
> +		.capabilities	=3D CEDRUS_CAPABILITY_H265_DEC,
>  	},
>  	{
>  		.cfg =3D {
> @@ -197,7 +197,7 @@ static const struct cedrus_control cedrus_controls[] =
=3D {
>  			.max =3D 0xffffffff,
>  			.step =3D 1,
>  		},
> -		.codec		=3D CEDRUS_CODEC_H265,
> +		.capabilities	=3D CEDRUS_CAPABILITY_H265_DEC,
>  	},
>  	{
>  		.cfg =3D {
> @@ -205,7 +205,7 @@ static const struct cedrus_control cedrus_controls[] =
=3D {
>  			.max	=3D V4L2_STATELESS_HEVC_DECODE_MODE_SLICE_BASED,
>  			.def	=3D V4L2_STATELESS_HEVC_DECODE_MODE_SLICE_BASED,
>  		},
> -		.codec		=3D CEDRUS_CODEC_H265,
> +		.capabilities	=3D CEDRUS_CAPABILITY_H265_DEC,
>  	},
>  	{
>  		.cfg =3D {
> @@ -213,19 +213,19 @@ static const struct cedrus_control cedrus_controls[=
] =3D {
>  			.max	=3D V4L2_STATELESS_HEVC_START_CODE_NONE,
>  			.def	=3D V4L2_STATELESS_HEVC_START_CODE_NONE,
>  		},
> -		.codec		=3D CEDRUS_CODEC_H265,
> +		.capabilities	=3D CEDRUS_CAPABILITY_H265_DEC,
>  	},
>  	{
>  		.cfg =3D {
>  			.id	=3D V4L2_CID_STATELESS_VP8_FRAME,
>  		},
> -		.codec		=3D CEDRUS_CODEC_VP8,
> +		.capabilities	=3D CEDRUS_CAPABILITY_VP8_DEC,
>  	},
>  	{
>  		.cfg =3D {
>  			.id =3D V4L2_CID_STATELESS_HEVC_DECODE_PARAMS,
>  		},
> -		.codec		=3D CEDRUS_CODEC_H265,
> +		.capabilities	=3D CEDRUS_CAPABILITY_H265_DEC,
>  	},
>  };
> =20
> @@ -275,6 +275,9 @@ static int cedrus_init_ctrls(struct cedrus_dev *dev, =
struct cedrus_ctx *ctx)
>  		return -ENOMEM;
> =20
>  	for (i =3D 0; i < CEDRUS_CONTROLS_COUNT; i++) {
> +		if (!cedrus_is_capable(ctx, cedrus_controls[i].capabilities))
> +			continue;
> +
>  		ctrl =3D v4l2_ctrl_new_custom(hdl, &cedrus_controls[i].cfg,
>  					    NULL);
>  		if (hdl->error) {
> diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/stagin=
g/media/sunxi/cedrus/cedrus.h
> index 1a98790a99af..7a1619967513 100644
> --- a/drivers/staging/media/sunxi/cedrus/cedrus.h
> +++ b/drivers/staging/media/sunxi/cedrus/cedrus.h
> @@ -57,7 +57,7 @@ enum cedrus_h264_pic_type {
> =20
>  struct cedrus_control {
>  	struct v4l2_ctrl_config cfg;
> -	enum cedrus_codec	codec;
> +	unsigned int		capabilities;
>  };
> =20
>  struct cedrus_h264_run {
> --=20
> 2.38.1
>=20

--=20
Paul Kocialkowski, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com

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