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Message-ID: <93932c6b-4be1-3c3c-2cef-e97fe9415745@ti.com>
Date:   Wed, 26 Oct 2022 11:43:36 +0530
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To:     Tony Lindgren <tony@atomide.com>,
        =?UTF-8?Q?Ilpo_J=c3=a4rvinen?= <ilpo.jarvinen@linux.intel.com>
CC:     Sebastian Andrzej Siewior <bigeasy@linutronix.de>,
        Matthias Schiffer <matthias.schiffer@ew.tq-group.com>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        Jiri Slaby <jirislaby@kernel.org>,
        Peter Hurley <peter@hurleysoftware.com>,
        linux-serial <linux-serial@vger.kernel.org>,
        LKML <linux-kernel@vger.kernel.org>, Nishanth Menon <nm@ti.com>,
        <linux-omap@vger.kernel.org>
References: <20221013112339.2540767-1-matthias.schiffer@ew.tq-group.com>
 <ea90b0ba-61bf-e56e-5120-9771122838cf@linux.intel.com>
 <Y00bmec4hvWxtnB5@linutronix.de>
 <c91216ec-c7e7-df7b-463-ec17c76b7bc2@linux.intel.com>
 <Y1YigD1lEWRbT8eH@atomide.com>
From:   Vignesh Raghavendra <vigneshr@ti.com>
Subject: Re: [PATCH] serial: 8250_omap: remove wait loop from Errata i202
 workaround
In-Reply-To: <Y1YigD1lEWRbT8eH@atomide.com>
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On 24/10/22 10:58 am, Tony Lindgren wrote:
> Hi,
> 
> Adding Nishanth to Cc also.
> 
> * Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> [221017 12:06]:
>> On Mon, 17 Oct 2022, Sebastian Andrzej Siewior wrote:
>>
>>> On 2022-10-17 11:12:41 [+0300], Ilpo Järvinen wrote:
>>>> On Thu, 13 Oct 2022, Matthias Schiffer wrote:
>>>>
>>>>> We were occasionally seeing the "Errata i202: timedout" on an AM335x
>>>>> board when repeatedly opening and closing a UART connected to an active
>>>>> sender. As new input may arrive at any time, it is possible to miss the
>>>>> "RX FIFO empty" condition, forcing the loop to wait until it times out.
>>>>
>>>> I can see this problem could occur and why your patch fixes it.
>>>>
>>>>> Nothing in the i202 Advisory states that such a wait is even necessary;
>>>>> other FIFO clear functions like serial8250_clear_fifos() do not wait
>>>>> either. For this reason, it seems safe to remove the wait, fixing the
>>>>> mentioned issue.
>>>>
>>>> Checking the commit that added this driver and the loop along with it, 
>>>> there was no information why it would be needed there either.
>>>
>>> I don't remember all the details but I do remember that I never hit it.
>>> The idea back then was to document what appears the problem and then
>>> once there is a reproducer address it _or_ when there is another problem
>>> check if it aligns with the output here (so that _this_ problem's origin
>>> could be this). This was part of address all known chip erratas and
>>> copied from omap-serial at the time so that the 8250 does not miss
>>> anything.
>>> Looking closer, this is still part of the omap-serial driver and it was
>>> introduced in commit
>>>    0003450964357 ("omap2/3/4: serial: errata i202: fix for MDR1 access")
>>
>> I found that one too but it doesn't give any explanation for it either.
>> In fact, the wait for empty is mysteriously missing from the itemized
>> description of the workaround in the commit message.
>>
>>> If someone found a way to trigger this output which is unrelated to the
>>> expected cause then this is clearly not helping nor intended.
>>>
>>> I would prefer to keep the loop and replace the disturbing output with a
>>> comment describing _why_ the FIFO might remain non-empty after a flush.
>>>
>>> In worst cases that loop causes a delay of less than 0.5ms while setting
>>> a baud rate so I doubt that this is causing a real problem.
> 
> This sounds like a safe solution for me if it's needed.
> 
>>> Either way I would like to see Tony's ACK before this is getting removed
>>> as suggested in this patch.
>>
>> Thanks for chimming in.
>>
>> I went to do some lore searching and came across this thread (it should 
>> be added with Link: tag the patch regardless of its final form):
>>   https://lore.kernel.org/linux-omap/4BBF61FE.3060807@ti.com/
> 
> Nishanth, do you have any more info on checking for fifo empty here?
> 

At least TRMs of newer SoCs such as AM654 [0] have following note:

NOTE : Bits UART_FCR[2] TX_FIFO_CLEAR and UART_FCR[1] RX_FIFO_CLEAR are

automatically cleared by hardware after 4 × UARTi_ICLK + 5 × UARTi_FCLK
clock cycles.

This delay is needed to finish the resetting of the corresponding FIFO
and DMA control
 registers.

I guess we can drop FIFO empty check and instead add above delay
required for FIFOs to be reset.

[0] https://www.ti.com/lit/pdf/spruid7e 12.1.5.4.6 UART FIFO Management


Regards
Vignesh