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[209.85.128.181]) by smtp.gmail.com with ESMTPSA id a25-20020a05620a16d900b006b615cd8c13sm3306437qkn.106.2022.10.26.00.58.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 26 Oct 2022 00:58:35 -0700 (PDT) Received: by mail-yw1-f181.google.com with SMTP id 00721157ae682-333a4a5d495so139335527b3.10; Wed, 26 Oct 2022 00:58:35 -0700 (PDT) X-Received: by 2002:a81:12c8:0:b0:36a:bd6b:92fb with SMTP id 191-20020a8112c8000000b0036abd6b92fbmr20336268yws.316.1666771114757; Wed, 26 Oct 2022 00:58:34 -0700 (PDT) MIME-Version: 1.0 References: <20221026014227.162121-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20221026014227.162121-3-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20221026014227.162121-3-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Geert Uytterhoeven Date: Wed, 26 Oct 2022 09:58:22 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 2/2] clk: renesas: r9a07g044: Add CRU_SYSCLK and CRU_VCLK to no PM list To: Prabhakar Cc: Michael Turquette , Stephen Boyd , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-1.6 required=5.0 tests=BAYES_00, FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Prabhakar, On Wed, Oct 26, 2022 at 3:42 AM Prabhakar wrote: > From: Lad Prabhakar > > CRU_SYSCLK and CRU_VCLK clocks need to be turned ON/OFF in particular > sequence for the CRU block hence add these clocks to > r9a07g044_no_pm_mod_clks[] array. > > Signed-off-by: Lad Prabhakar > --- > v1->v2 > * Dropped usage of DEF_NO_PM() macro > * Added CRU_SYSCLK and CRU_VCLK to no PM list > * Updated commit message Thanks for the update! > --- a/drivers/clk/renesas/r9a07g044-cpg.c > +++ b/drivers/clk/renesas/r9a07g044-cpg.c > @@ -412,6 +412,11 @@ static const unsigned int r9a07g044_crit_mod_clks[] __initconst = { > MOD_CLK_BASE + R9A07G044_DMAC_ACLK, > }; > > +static const unsigned int r9a07g044_no_pm_mod_clks[] __initconst = { This cannot be __initconst, so please drop this keyword. > + MOD_CLK_BASE + R9A07G044_CRU_SYSCLK, > + MOD_CLK_BASE + R9A07G044_CRU_VCLK, > +}; I believe I haven't seen patches yet to add support for these clocks? Perhaps these can be combined? Thanks! Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds