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[2620:137:e000::1:20]) by mx.google.com with ESMTP id m1-20020a17090a3f8100b001fd70129092si1087933pjc.15.2022.10.26.23.57.14; Wed, 26 Oct 2022 23:57:25 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b="AVgl+3v/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234240AbiJ0Gyl (ORCPT + 99 others); Thu, 27 Oct 2022 02:54:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34684 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234090AbiJ0Gyf (ORCPT ); Thu, 27 Oct 2022 02:54:35 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C82D2186; Wed, 26 Oct 2022 23:54:30 -0700 (PDT) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 29R2XZgL009987; Thu, 27 Oct 2022 06:53:59 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=message-id : date : mime-version : subject : to : cc : references : from : in-reply-to : content-type : content-transfer-encoding; s=qcppdkim1; bh=syPyurz2hhstTkkwRSZpYhXWSDh9wHm/gejEOlSajjk=; b=AVgl+3v/568Cp1vIrni/VEMkL8DuEj3qTPDsDIveNW+H6wiAuyuN/DcofVneP4KBhGJC OUtoiEPb4FVMpkY5A5+NMaB3zFowQPvRVHdE3NMFZcRzVZppMGR4eyW/mVu0+KPJ7Vyq DwzJMgtwtw4bF0G+pV2k5BcBnT84yPJmZm1kJmDnK9t/9SbgXtN0lwAIff+CdSnCtmTC QaiLiCKlXPmu3YByGz8m2RP4NNuaJEqqhSkuR5q/59KTbWqz1aDqthH/NMv1RUX63Zqb xhkX8OmkX3h7Rlqd9TaOlK/BITvGHegYTdz9TQrfRRW+/4D4cpKd34UONxUOxcH+OVRe hQ== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3kfahb9pgy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 Oct 2022 06:53:58 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 29R6rvJ8021266 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 Oct 2022 06:53:57 GMT Received: from [10.239.133.211] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Wed, 26 Oct 2022 23:53:53 -0700 Message-ID: <25966b5d-b7b0-8429-12b0-9fd394a6c25e@quicinc.com> Date: Thu, 27 Oct 2022 14:53:51 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.1.2 Subject: Re: [PATCH 5/9] coresight-tpdm: Add nodes to set trigger timestamp and type Content-Language: en-US To: Suzuki K Poulose , Mathieu Poirier , Alexander Shishkin , Konrad Dybcio , Mike Leach CC: Jinlong Mao , Leo Yan , "Greg Kroah-Hartman" , , , , Tingwei Zhang , Yuanfang Zhang , Trilok Soni , Hao Zhang , , References: <1662626705-13097-1-git-send-email-quic_taozha@quicinc.com> <1662626705-13097-6-git-send-email-quic_taozha@quicinc.com> From: Tao Zhang In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: jT53p6yzEgHTT1KXtcBPWMD_DBpvhjAE X-Proofpoint-ORIG-GUID: jT53p6yzEgHTT1KXtcBPWMD_DBpvhjAE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-27_03,2022-10-26_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 adultscore=0 mlxscore=0 suspectscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 priorityscore=1501 mlxlogscore=999 clxscore=1015 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2210170000 definitions=main-2210270037 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Suzuki, 在 10/24/2022 6:32 PM, Suzuki K Poulose 写道: > On 08/09/2022 09:45, Tao Zhang wrote: >> The nodes are needed to set or show the trigger timestamp and >> trigger type. This change is to add these nodes to achieve these >> function. >> >> Signed-off-by: Tao Zhang >> --- >>   drivers/hwtracing/coresight/coresight-tpdm.c | 90 >> ++++++++++++++++++++++++++++ >>   1 file changed, 90 insertions(+) >> >> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c >> b/drivers/hwtracing/coresight/coresight-tpdm.c >> index 74cc653..fae9963 100644 >> --- a/drivers/hwtracing/coresight/coresight-tpdm.c >> +++ b/drivers/hwtracing/coresight/coresight-tpdm.c >> @@ -232,8 +232,98 @@ static struct attribute_group tpdm_attr_grp = { >>       .attrs = tpdm_attrs, >>   }; >>   +static ssize_t dsb_trig_type_show(struct device *dev, >> +                     struct device_attribute *attr, >> +                     char *buf) >> +{ >> +    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); >> + >> +    if (!(drvdata->datasets & TPDM_PIDR0_DS_DSB)) >> +        return -EPERM; >> + >> +    return scnprintf(buf, PAGE_SIZE, "%u\n", >> +             (unsigned int)drvdata->dsb->trig_type); >> +} >> + >> +/* >> + * value 0: set trigger type as enablement >> + * value 1: set trigger type as disablement >> + */ >> +static ssize_t dsb_trig_type_store(struct device *dev, >> +                      struct device_attribute *attr, >> +                      const char *buf, >> +                      size_t size) >> +{ >> +    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); >> +    unsigned long val; >> + >> +    if ((kstrtoul(buf, 16, &val)) || val < 0 || val > 1) >> +        return -EINVAL; >> +    if (!(drvdata->datasets & TPDM_PIDR0_DS_DSB)) >> +        return -EPERM; >> + >> +    spin_lock(&drvdata->spinlock); >> +    if (val) >> +        drvdata->dsb->trig_type = true; >> +    else >> +        drvdata->dsb->trig_type = false; >> +    spin_unlock(&drvdata->spinlock); >> +    return size; >> +} >> +static DEVICE_ATTR_RW(dsb_trig_type); >> + >> +static ssize_t dsb_trig_ts_show(struct device *dev, >> +                     struct device_attribute *attr, >> +                     char *buf) >> +{ >> +    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); >> + >> +    if (!(drvdata->datasets & TPDM_PIDR0_DS_DSB)) >> +        return -EPERM; >> + >> +    return scnprintf(buf, PAGE_SIZE, "%u\n", >> +             (unsigned int)drvdata->dsb->trig_ts); >> +} >> + >> +/* >> + * value 0: set trigger timestamp as enablement >> + * value 1: set trigger timestamp as disablement >> + */ >> +static ssize_t dsb_trig_ts_store(struct device *dev, >> +                      struct device_attribute *attr, >> +                      const char *buf, >> +                      size_t size) >> +{ >> +    struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent); >> +    unsigned long val; >> + >> +    if ((kstrtoul(buf, 16, &val)) || val < 0 || val > 1) >> +        return -EINVAL; >> +    if (!(drvdata->datasets & TPDM_PIDR0_DS_DSB)) >> +        return -EPERM; >> + >> +    spin_lock(&drvdata->spinlock); >> +    if (val) >> +        drvdata->dsb->trig_ts = true; >> +    else >> +        drvdata->dsb->trig_ts = false; >> +    spin_unlock(&drvdata->spinlock); >> +    return size; >> +} >> +static DEVICE_ATTR_RW(dsb_trig_ts); >> +static struct attribute *tpdm_dsb_attrs[] = { >> +    &dev_attr_dsb_trig_ts.attr, >> +    &dev_attr_dsb_trig_type.attr, >> +    NULL, >> +}; >> + >> +static struct attribute_group tpdm_dsb_attr_grp = { >> +    .attrs = tpdm_dsb_attrs, >> +}; >> + > > Please could we hide the "DSB" related knobs, if the > the Data sets are missing using is_visible() hook ? > Make sense, I will update this in the next patch series. > Suzuki > Best Regards Tao