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From:   Jianmin Lv <lvjianmin@loongson.cn>
To:     Huacai Chen <chenhuacai@kernel.org>,
        WANG Xuerui <kernel@xen0n.name>
Cc:     linux-kernel@vger.kernel.org, loongarch@lists.linux.dev
Subject: [PATCH V2] LoongArch: Fix memsection size
Date:   Thu, 27 Oct 2022 20:47:32 +0800
Message-Id: <20221027124732.20837-1-lvjianmin@loongson.cn>
MIME-Version: 1.0
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On LoongArch, the physical address (0 - 0xfff_ffff) is always memory, which
is in the low half of the memsection (0 - 0x1fff_ffff) with 512M size, and
the high half will be a hole which is not memory but I/O registers (of cpu
and chipset).

This situation may cause some issues. For example, during S3, these I/O registers
will be saved and restored as valid memory pages (pfn_valid() of common version
returns true for the whole memsection) which will cause exception, especially
on resume.

To avoid exceptions, we can use 256M memsection size, or use the way as ARM64 to
walk through all memory memblock to check if a mem pfn is valid which maybe
lower performance. For simplicity, this patch just use the former way.

Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>

diff --git a/arch/loongarch/include/asm/sparsemem.h b/arch/loongarch/include/asm/sparsemem.h
index 3d18cdf1b069..05903b40a625 100644
--- a/arch/loongarch/include/asm/sparsemem.h
+++ b/arch/loongarch/include/asm/sparsemem.h
@@ -8,7 +8,7 @@
  * SECTION_SIZE_BITS		2^N: how big each section will be
  * MAX_PHYSMEM_BITS		2^N: how much memory we can have in that space
  */
-#define SECTION_SIZE_BITS	29 /* 2^29 = Largest Huge Page Size */
+#define SECTION_SIZE_BITS	28
 #define MAX_PHYSMEM_BITS	48
 
 #endif /* CONFIG_SPARSEMEM */
-- 
2.31.1