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Date:   Thu, 27 Oct 2022 13:40:17 +0100
From:   Paul Cercueil <paul@crapouillou.net>
Subject: Re: [PATCH v2 3/6] clk: ingenic: Add .set_rate_hook() for PLL clocks
To:     Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Cc:     mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, zhouyu@wanyeetech.com,
        linux-mips@vger.kernel.org, linux-clk@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
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        <20221026194345.243007-4-aidanmacdonald.0x0@gmail.com>
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Hi Aidan,

Le mer. 26 oct. 2022 =E0 20:43:42 +0100, Aidan MacDonald=20
<aidanmacdonald.0x0@gmail.com> a =E9crit :
> The set rate hook is called immediately after updating the clock
> register but before the spinlock is released. This allows another
> register to be updated alongside the main one, which is needed to
> handle the I2S divider on some SoCs.
>=20
> Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>

Reviewed-by: Paul Cercueil <paul@crapouillou.net>

Cheers,
-Paul

> ---
>  drivers/clk/ingenic/cgu.c | 3 +++
>  drivers/clk/ingenic/cgu.h | 4 ++++
>  2 files changed, 7 insertions(+)
>=20
> diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c
> index aea01b6b2764..b6a4d4236c16 100644
> --- a/drivers/clk/ingenic/cgu.c
> +++ b/drivers/clk/ingenic/cgu.c
> @@ -232,6 +232,9 @@ ingenic_pll_set_rate(struct clk_hw *hw, unsigned=20
> long req_rate,
>=20
>  	writel(ctl, cgu->base + pll_info->reg);
>=20
> +	if (pll_info->set_rate_hook)
> +		pll_info->set_rate_hook(pll_info, rate, parent_rate);
> +
>  	/* If the PLL is enabled, verify that it's stable */
>  	if (pll_info->enable_bit >=3D 0 && (ctl & BIT(pll_info->enable_bit)))
>  		ret =3D ingenic_pll_check_stable(cgu, pll_info);
> diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h
> index a5e44ca7f969..99da9bd86e63 100644
> --- a/drivers/clk/ingenic/cgu.h
> +++ b/drivers/clk/ingenic/cgu.h
> @@ -46,6 +46,8 @@
>   *		-1 if there is no enable bit (ie, the PLL is always on)
>   * @stable_bit: the index of the stable bit in the PLL control=20
> register, or
>   *		-1 if there is no stable bit
> + * @set_rate_hook: hook called immediately after updating the CGU=20
> register,
> + *		   before releasing the spinlock
>   */
>  struct ingenic_cgu_pll_info {
>  	unsigned reg;
> @@ -61,6 +63,8 @@ struct ingenic_cgu_pll_info {
>  	void (*calc_m_n_od)(const struct ingenic_cgu_pll_info *pll_info,
>  			    unsigned long rate, unsigned long parent_rate,
>  			    unsigned int *m, unsigned int *n, unsigned int *od);
> +	void (*set_rate_hook)(const struct ingenic_cgu_pll_info *pll_info,
> +			      unsigned long rate, unsigned long parent_rate);
>  };
>=20
>  /**
> --
> 2.38.1
>=20