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From:   Chen-Yu Tsai <wenst@chromium.org>
Date:   Thu, 27 Oct 2022 10:48:26 -0700
Message-ID: <CAGXv+5Hki=VsvZrtANujFYseBp0Lxj4WVf3nzT7cx1kkMmWPFg@mail.gmail.com>
Subject: Re: [PATCH v2 2/4] ASoC: dt-bindings: realtek, rt5682s: Add AVDD and
 MICVDD supplies
To:     =?UTF-8?B?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= 
        <nfraprado@collabora.com>
Cc:     Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Rob Herring <robh+dt@kernel.org>,
        Mark Brown <broonie@kernel.org>, devicetree@vger.kernel.org,
        alsa-devel@alsa-project.org, Liam Girdwood <lgirdwood@gmail.com>,
        linux-kernel@vger.kernel.org, Derek Fang <derek.fang@realtek.com>,
        kernel@collabora.com,
        AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@collabora.com>
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On Thu, Oct 27, 2022 at 7:36 AM N=C3=ADcolas F. R. A. Prado
<nfraprado@collabora.com> wrote:
>
> On Tue, Oct 25, 2022 at 01:12:49PM -0700, Chen-Yu Tsai wrote:
> > On Mon, Oct 24, 2022 at 3:01 PM N=C3=ADcolas F. R. A. Prado
> > <nfraprado@collabora.com> wrote:
> > >
> > > The rt5682s codec can have two supplies: AVDD and MICVDD. They are
> >
> > The actual chip also has LDO1_IN (for digital core and charge pump)
> > and DBVDD (for I/O). However in the Chromebook designs these two
> > and AVDD are all provided from the same power rail, through separate
> > filter banks.
>
> What about rt5682 (no s), does that chip also have these same supplies?
>
> Also, since you already gave the purpose of these other supplies, could y=
ou also
> tell the purpose of AVDD, MICVDD and (for rt5682) VBAT? That way I could =
add
> some description for them in the binding.

As Mark mentioned in his reply, these are quite standard names.

AVDD is for the analog bits. MICVDD is for the microphone bias.
VBAT is called battery power in the datasheet. The block diagram
shows it going through an internal controllable LDO whose output
then powers MICVDD. This could be used in designs that don't
include a suitable external supply for MICVDD. If MICVDD is provided,
then one would turn the internal LDO off.

So either VBAT or MICVDD has to be provided.

ChenYu

> Thanks,
> N=C3=ADcolas
>
> >
> > Neither does the datasheet specify the ordering of AVDD, DBVDD, and
> > LDO1_IN for power sequencing, just that three should be toggled togethe=
r.
> >
> > Should we model these? Or wait until some design actually splits these?
> [..]