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charset="us-ascii" Content-ID: MIME-Version: 1.0 X-OriginatorOrg: meta.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CO1PR15MB4969.namprd15.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: d181e877-f643-4e91-ba27-08dab89193a4 X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Oct 2022 03:07:41.2692 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 8ae927fe-1255-47a7-a2af-5f3a069daaa2 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: EyXGqlC49jzT5H2rPqiMYLWOYadfJWz+Yw0bDEyrxpyiORHXNfXLMKfJf9PFefy4WlG+VdTMEy8lrC2x0lNAfg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR15MB2553 X-Proofpoint-GUID: PQPFcz1zDgSkalnBTi8ef8mWeeINXwZS X-Proofpoint-ORIG-GUID: PQPFcz1zDgSkalnBTi8ef8mWeeINXwZS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.545,FMLib:17.11.122.1 definitions=2022-10-27_07,2022-10-27_01,2022-06-22_01 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > On Oct 26, 2022, at 12:31 PM, Smita Koralahalli wrote: > > On 10/25/2022 5:11 PM, Dan Williams wrote: >> Smita Koralahalli wrote: >>> Hi Dan, >>> >>> On 10/21/2022 3:18 PM, Dan Williams wrote: >>>> Hi Smita, >>>> >>>> Smita Koralahalli wrote: >>>>> This series adds decoding for the CXL Protocol Errors Common Platform >>>>> Error Record. >>>> Be sure to copy Ard Biesheuvel , added, on >>>> drivers/firmware/efi/ patches. >>>> >>>> Along those lines, drivers/cxl/ developers have an idea of what is >>>> contained in the new CXL protocol error records and why Linux might want >>>> to decode them, others from outside drivers/cxl/ might not. It always >>>> helps to have a small summary of the benefit to end users of the >>>> motivation to apply a patch set. >>> Sure, will include in my v2. >>> >>>>> Smita Koralahalli (2): >>>>> efi/cper, cxl: Decode CXL Protocol Error Section >>>>> efi/cper, cxl: Decode CXL Error Log >>>>> >>>>> drivers/firmware/efi/Makefile | 2 +- >>>>> drivers/firmware/efi/cper.c | 9 +++ >>>>> drivers/firmware/efi/cper_cxl.c | 108 ++++++++++++++++++++++++++++++++ >>>>> drivers/firmware/efi/cper_cxl.h | 58 +++++++++++++++++ >>>>> include/linux/cxl_err.h | 21 +++++++ >>>>> 5 files changed, 197 insertions(+), 1 deletion(-) >>>> I notice no updates for the trace events in ghes_do_proc(), is that next >>>> in your queue? That's ok to be a follow-on after v2. >>> Sorry, if I haven't understood this right. Are you implying about the >>> "handling" >>> of cxl memory errors in ghes_do_proc() or is it just copying of CPER >>> entries to >>> tracepoints? >> Right now ghes_do_proc() will let the CXL CPER records fall through to >> log_non_standard_event(). Are you planning to add trace event decode >> there for CPER_SEC_CXL_PROT_ERR records? > > Thanks! Yeah its a good idea to add. I did not think about this before. > I will send this as a separate patchset after v2. > > I think with this cxl cper trace event support and Ira's patchset which traces > specific event record types via Get Event Record, we can start the userspace > handling probably in rasdaemon? Yes, I think this makes sense. rasdaemon could aggregate data and provide user with full picture: * Memory errors from both processor attached memory and CXL memory. * CXL protocol errors. * CXL device errors. Such errors may be handled either firmware first or OS first. > >> >> I am not sure if the CXL CPER to trace record conversion belongs there, >> or somewhere closer to trace_aer_event() invocations since the CXL >> protocol errors are effectively an extenstion of PCI AER events. > > Right, I will keep it simple in v1 and get the comments about the placement.. > > Thanks, > Smita > > >