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From:   Sarath Babu Naidu Gaddam <sarath.babu.naidu.gaddam@amd.com>
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        <harini.katakam@amd.com>, <sarath.babu.naidu.gaddam@amd.com>,
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Subject: [PATCH 0/5] Xilinx DMA enhancements and optimization 
Date:   Thu, 27 Oct 2022 23:09:35 -0600
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Some background about the patch series: Xilinx Axi Ethernet device driver
(xilinx_axienet_main.c) currently has axi-dma code inside it. The goal is
to refactor axiethernet driver and use existing AXI DMA driver using
DMAEngine API.

This patchset does feature addition and optimization to support axidma
integration with axiethernet network driver. Once axidma version is
accepted mcdma specific changes will be added in followup version.

Radhey Shyam Pandey (5):
  dt-bindings: dmaengine: xilinx_dma: Add xlnx,axistream-connected
    property
  dt-bindings: dmaengine: xilinx_dma: Add xlnx,irq-delay property
  dmaengine: xilinx_dma: Pass AXI4-Stream control words to dma client
  dmaengine: xilinx_dma: Increase AXI DMA transaction segment count
  dmaengine: xilinx_dma: Use tasklet_hi_schedule for timing critical
    usecase

 .../bindings/dma/xilinx/xilinx_dma.txt        |  4 ++
 drivers/dma/xilinx/xilinx_dma.c               | 41 ++++++++++++++++++-
 2 files changed, 43 insertions(+), 2 deletions(-)

-- 
2.25.1