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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MN0PR12MB5953.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: a3747310-0280-421e-c3e1-08dab8b470f0 X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Oct 2022 07:17:15.4484 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 3KGbaJXUY/QU/r0p6VjzdoB2CRV/UoLLSxmiWXYDYyW042FRO4AgTZ7bq1MA5/Zz X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6444 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Sarath Babu Naidu Gaddam > Sent: Friday, October 28, 2022 10:40 AM > To: vkoul@kernel.org; robh+dt@kernel.org; > krzysztof.kozlowski+dt@linaro.org; lars@metafoo.de; > adrianml@alumnos.upm.es > Cc: dmaengine@vger.kernel.org; devicetree@vger.kernel.org; linux-arm- > kernel@lists.infradead.org; linux-kernel@vger.kernel.org; Simek, Michal > ; Pandey, Radhey Shyam > ; Sarangi, Anirudha > ; Katakam, Harini > ; Gaddam, Sarath Babu Naidu > ; git (AMD-Xilinx) > Subject: [PATCH 3/5] dmaengine: xilinx_dma: Pass AXI4-Stream control > words to dma client >=20 > From: Radhey Shyam Pandey >=20 > Read DT property to check if AXI DMA is connected to streaming IP i.e > axiethernet. If connected pass AXI4-Stream control words to dma client us= ing > metadata_ops dmaengine API. >=20 > Signed-off-by: Radhey Shyam Pandey > Signed-off-by: Sarath Babu Naidu Gaddam > > --- > drivers/dma/xilinx/xilinx_dma.c | 37 > +++++++++++++++++++++++++++++++++ > 1 file changed, 37 insertions(+) >=20 > diff --git a/drivers/dma/xilinx/xilinx_dma.c > b/drivers/dma/xilinx/xilinx_dma.c index 8cd4e69dc7b4..b69e0482a50f > 100644 > --- a/drivers/dma/xilinx/xilinx_dma.c > +++ b/drivers/dma/xilinx/xilinx_dma.c > @@ -493,6 +493,7 @@ struct xilinx_dma_config { > * @s2mm_chan_id: DMA s2mm channel identifier > * @mm2s_chan_id: DMA mm2s channel identifier > * @max_buffer_len: Max buffer length > + * @has_axistream_connected: AXI DMA connected to AXI Stream IP > */ > struct xilinx_dma_device { > void __iomem *regs; > @@ -511,6 +512,7 @@ struct xilinx_dma_device { > u32 s2mm_chan_id; > u32 mm2s_chan_id; > u32 max_buffer_len; > + bool has_axistream_connected; > }; >=20 > /* Macros */ > @@ -623,6 +625,29 @@ static inline void xilinx_aximcdma_buf(struct > xilinx_dma_chan *chan, > } > } >=20 > +/** > + * xilinx_dma_get_metadata_ptr- Populate metadata pointer and payload > +length > + * @tx: async transaction descriptor > + * @payload_len: metadata payload length > + * @max_len: metadata max length > + * Return: The app field pointer. > + */ > +static void *xilinx_dma_get_metadata_ptr(struct dma_async_tx_descriptor > *tx, > + size_t *payload_len, size_t > *max_len) { > + struct xilinx_dma_tx_descriptor *desc =3D to_dma_tx_descriptor(tx); > + struct xilinx_axidma_tx_segment *seg; > + > + *max_len =3D *payload_len =3D sizeof(u32) * > XILINX_DMA_NUM_APP_WORDS; > + seg =3D list_first_entry(&desc->segments, > + struct xilinx_axidma_tx_segment, node); > + return seg->hw.app; > +} > + > +static struct dma_descriptor_metadata_ops xilinx_dma_metadata_ops =3D { > + .get_ptr =3D xilinx_dma_get_metadata_ptr, }; > + > /* ---------------------------------------------------------------------= -------- > * Descriptors and segments alloc and free > */ > @@ -2326,6 +2351,9 @@ static struct dma_async_tx_descriptor > *xilinx_dma_prep_dma_cyclic( > segment->hw.control |=3D XILINX_DMA_BD_EOP; > } >=20 > + if (chan->xdev->has_axistream_connected) > + desc->async_tx.metadata_ops =3D &xilinx_dma_metadata_ops; > + > return &desc->async_tx; >=20 > error: > @@ -3065,6 +3093,11 @@ static int xilinx_dma_probe(struct > platform_device *pdev) > } > } >=20 > + if (xdev->dma_config->dmatype =3D=3D XDMA_TYPE_AXIDMA) { xlnx,axistream-connected is an optional property for both AXIDMA and MCDMA. Please extend its implementation for the MCDMA support. > + xdev->has_axistream_connected =3D > + of_property_read_bool(node, "xlnx,axistream- > connected"); > + } > + > if (xdev->dma_config->dmatype =3D=3D XDMA_TYPE_VDMA) { > err =3D of_property_read_u32(node, "xlnx,num-fstores", > &num_frames); > @@ -3090,6 +3123,10 @@ static int xilinx_dma_probe(struct > platform_device *pdev) > else > xdev->ext_addr =3D false; >=20 > + /* Set metadata mode */ > + if (xdev->has_axistream_connected) > + xdev->common.desc_metadata_modes =3D > DESC_METADATA_ENGINE; > + > /* Set the dma mask bits */ > err =3D dma_set_mask_and_coherent(xdev->dev, > DMA_BIT_MASK(addr_width)); > if (err < 0) { > -- > 2.25.1