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[209.85.219.178]) by smtp.gmail.com with ESMTPSA id y2-20020a05620a44c200b006ce76811a07sm2772434qkp.75.2022.10.28.04.35.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 28 Oct 2022 04:35:14 -0700 (PDT) Received: by mail-yb1-f178.google.com with SMTP id m125so5796326ybb.6; Fri, 28 Oct 2022 04:35:13 -0700 (PDT) X-Received: by 2002:a25:d64e:0:b0:6cb:7faa:af94 with SMTP id n75-20020a25d64e000000b006cb7faaaf94mr16836632ybg.36.1666956913602; Fri, 28 Oct 2022 04:35:13 -0700 (PDT) MIME-Version: 1.0 References: <20221025220629.79321-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20221025220629.79321-3-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20221025220629.79321-3-prabhakar.mahadev-lad.rj@bp.renesas.com> From: Geert Uytterhoeven Date: Fri, 28 Oct 2022 13:35:01 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 2/2] arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts To: Prabhakar Cc: Magnus Damm , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Arnd Bergmann , Olof Johansson , Conor Dooley , Samuel Holland , soc@kernel.org, linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Biju Das , Lad Prabhakar Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=-1.6 required=5.0 tests=BAYES_00, FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Prabhakar, On Wed, Oct 26, 2022 at 12:06 AM Prabhakar wrote: > From: Lad Prabhakar > > Move RZ/G2UL SoC specific parts to r9a07g043u.dtsi so that r9a07g043.dtsi > can be shared with RZ/Five (RISC-V SoC). > > Below are the changes due to which SoC specific parts are moved to > r9a07g043u.dtsi: > - RZ/G2UL has Cortex-A55 (ARM64) whereas the RZ/Five has AX45MP (RISC-V) > - RZ/G2UL has GICv3 as interrupt controller whereas the RZ/Five has PLIC > - RZ/G2UL has interrupts for SYSC block whereas interrupts are missing > for SYSC block on RZ/Five > - RZ/G2UL has armv8-timer whereas the RZ/Five has riscv-timer > > Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven i.e. will queue in renesas-devel for v6.2. > --- > RFC->v2 > * Updated commit message about timer Right. And I'll add while applying: - RZ/G2UL has PSCI whereas RZ/Five have OpenSBI Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds