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Date:   Mon, 31 Oct 2022 09:56:20 +0100
Message-Id: <CNZZEPIA4LGS.EFHSXO9SRUSH@otso>
Cc:     <~postmarketos/upstreaming@lists.sr.ht>,
        "AngeloGioacchino Del Regno" 
        <angelogioacchino.delregno@somainline.org>,
        "Konrad Dybcio" <konrad.dybcio@somainline.org>,
        "Martin Botka" <martin.botka@somainline.org>,
        "Jami Kettunen" <jami.kettunen@somainline.org>,
        "Andy Gross" <agross@kernel.org>,
        "Bjorn Andersson" <andersson@kernel.org>,
        "Rob Herring" <robh+dt@kernel.org>,
        "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
        "Luca Weiss" <luca@z3ntu.xyz>, <linux-arm-msm@vger.kernel.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 02/10] arm64: dts: qcom: sm6350: Add pinctrl for SDHCI 2
From:   "Luca Weiss" <luca.weiss@fairphone.com>
To:     "Marijn Suijten" <marijn.suijten@somainline.org>,
        <phone-devel@vger.kernel.org>
References: <20221030073232.22726-1-marijn.suijten@somainline.org>
 <20221030073232.22726-3-marijn.suijten@somainline.org>
In-Reply-To: <20221030073232.22726-3-marijn.suijten@somainline.org>
Precedence: bulk

On Sun Oct 30, 2022 at 8:32 AM CET, Marijn Suijten wrote:
> Use the generic pin functions specifically for sdc2.
>
> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>

Reviewed-by: Luca Weiss <luca.weiss@fairphone.com>
Tested-by: Luca Weiss <luca.weiss@fairphone.com> # sm7225-fairphone-fp4

Regards
Luca

> ---
>  arch/arm64/boot/dts/qcom/sm6350.dtsi | 44 ++++++++++++++++++++++++++++
>  1 file changed, 44 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/q=
com/sm6350.dtsi
> index a3ae765d9781..b98b881ebe7e 100644
> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> @@ -1074,6 +1074,10 @@ sdhc_2: mmc@8804000 {
>  					<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>;
>  			interconnect-names =3D "sdhc-ddr", "cpu-sdhc";
> =20
> +			pinctrl-0 =3D <&sdc2_on_state>;
> +			pinctrl-1 =3D <&sdc2_off_state>;
> +			pinctrl-names =3D "default", "sleep";
> +
>  			qcom,dll-config =3D <0x0007642c>;
>  			qcom,ddr-config =3D <0x80040868>;
>  			power-domains =3D <&rpmhpd SM6350_CX>;
> @@ -1316,6 +1320,46 @@ tlmm: pinctrl@f100000 {
>  			#interrupt-cells =3D <2>;
>  			gpio-ranges =3D <&tlmm 0 0 157>;
> =20
> +			sdc2_off_state: sdc2-off-state {
> +				clk-pins {
> +					pins =3D "sdc2_clk";
> +					drive-strength =3D <2>;
> +					bias-disable;
> +				};
> +
> +				cmd-pins {
> +					pins =3D "sdc2_cmd";
> +					drive-strength =3D <2>;
> +					bias-pull-up;
> +				};
> +
> +				data-pins {
> +					pins =3D "sdc2_data";
> +					drive-strength =3D <2>;
> +					bias-pull-up;
> +				};
> +			};
> +
> +			sdc2_on_state: sdc2-on-state {
> +				clk-pins {
> +					pins =3D "sdc2_clk";
> +					drive-strength =3D <16>;
> +					bias-disable;
> +				};
> +
> +				cmd-pins {
> +					pins =3D "sdc2_cmd";
> +					drive-strength =3D <10>;
> +					bias-pull-up;
> +				};
> +
> +				data-pins {
> +					pins =3D "sdc2_data";
> +					drive-strength =3D <10>;
> +					bias-pull-up;
> +				};
> +			};
> +
>  			qup_uart9_default: qup-uart9-default-state {
>  				pins =3D "gpio25", "gpio26";
>  				function =3D "qup13_f2";
> --=20
> 2.38.1