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From:   Gaosheng Cui <cuigaosheng1@huawei.com>
To:     <tglx@linutronix.de>, <mingo@redhat.com>, <bp@alien8.de>,
        <dave.hansen@linux.intel.com>, <x86@kernel.org>, <hpa@zytor.com>,
        <tony.luck@intel.com>, <pawan.kumar.gupta@linux.intel.com>,
        <pbonzini@redhat.com>, <chenyi.qiang@intel.com>,
        <jithu.joseph@intel.com>, <alexs@kernel.org>,
        <cuigaosheng1@huawei.com>
CC:     <linux-kernel@vger.kernel.org>
Subject: [PATCH] x86/cpu: fix undefined behavior in bit shift for intel_detect_tlb
Date:   Mon, 31 Oct 2022 19:43:40 +0800
Message-ID: <20221031114340.4185587-1-cuigaosheng1@huawei.com>
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Shifting signed 32-bit value by 31 bits is undefined, so changing
significant bit to unsigned. The UBSAN warning calltrace like below:

UBSAN: shift-out-of-bounds in arch/x86/kernel/cpu/intel.c:948:21
left shift of 1 by 31 places cannot be represented in type 'int'
Call Trace:
 <TASK>
 dump_stack_lvl+0x7d/0xa5
 dump_stack+0x15/0x1b
 ubsan_epilogue+0xe/0x4e
 __ubsan_handle_shift_out_of_bounds+0x1e7/0x20c
 intel_detect_tlb+0x114/0xbd0
 identify_boot_cpu+0x29/0x9e
 check_bugs+0x2f/0x15a5
 start_kernel+0xc3f/0xc78
 x86_64_start_reservations+0x24/0x2a
 x86_64_start_kernel+0xed/0xf8
 secondary_startup_64_no_verify+0xe5/0xeb
 </TASK>

Fixes: e0ba94f14f74 ("x86/tlb_info: get last level TLB entry number of CPU")
Signed-off-by: Gaosheng Cui <cuigaosheng1@huawei.com>
---
 arch/x86/kernel/cpu/intel.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 2d7ea5480ec3..121c1c38162a 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -945,7 +945,7 @@ static void intel_detect_tlb(struct cpuinfo_x86 *c)
 
 		/* If bit 31 is set, this is an unknown format */
 		for (j = 0 ; j < 3 ; j++)
-			if (regs[j] & (1 << 31))
+			if (regs[j] & (1U << 31))
 				regs[j] = 0;
 
 		/* Byte 0 is level count, not a descriptor */
-- 
2.25.1