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[2620:137:e000::1:20]) by mx.google.com with ESMTP id b23-20020aa7cd17000000b0046272b487cesi6985866edw.331.2022.10.31.14.43.55; Mon, 31 Oct 2022 14:44:23 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230199AbiJaVMZ (ORCPT + 99 others); Mon, 31 Oct 2022 17:12:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230187AbiJaVMY (ORCPT ); Mon, 31 Oct 2022 17:12:24 -0400 Received: from relay06.th.seeweb.it (relay06.th.seeweb.it [5.144.164.167]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9A08914027 for ; Mon, 31 Oct 2022 14:12:23 -0700 (PDT) Received: from [192.168.1.101] (95.49.29.156.neoplus.adsl.tpnet.pl [95.49.29.156]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by m-r2.th.seeweb.it (Postfix) with ESMTPSA id 3743F3EAF0; Mon, 31 Oct 2022 22:12:21 +0100 (CET) Message-ID: <75ec7c4d-a238-a5d9-cffe-a1d24d08691d@somainline.org> Date: Mon, 31 Oct 2022 22:12:20 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.1 Subject: Re: [PATCH 02/10] arm64: dts: qcom: sm6350: Add pinctrl for SDHCI 2 Content-Language: en-US To: Marijn Suijten , phone-devel@vger.kernel.org Cc: ~postmarketos/upstreaming@lists.sr.ht, AngeloGioacchino Del Regno , Martin Botka , Jami Kettunen , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Luca Weiss , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20221030073232.22726-1-marijn.suijten@somainline.org> <20221030073232.22726-3-marijn.suijten@somainline.org> From: Konrad Dybcio In-Reply-To: <20221030073232.22726-3-marijn.suijten@somainline.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,NICE_REPLY_A, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 30.10.2022 08:32, Marijn Suijten wrote: > Use the generic pin functions specifically for sdc2. > > Signed-off-by: Marijn Suijten > --- Reviewed-by: Konrad Dybcio Konrad > arch/arm64/boot/dts/qcom/sm6350.dtsi | 44 ++++++++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi > index a3ae765d9781..b98b881ebe7e 100644 > --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi > @@ -1074,6 +1074,10 @@ sdhc_2: mmc@8804000 { > <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>; > interconnect-names = "sdhc-ddr", "cpu-sdhc"; > > + pinctrl-0 = <&sdc2_on_state>; > + pinctrl-1 = <&sdc2_off_state>; > + pinctrl-names = "default", "sleep"; > + > qcom,dll-config = <0x0007642c>; > qcom,ddr-config = <0x80040868>; > power-domains = <&rpmhpd SM6350_CX>; > @@ -1316,6 +1320,46 @@ tlmm: pinctrl@f100000 { > #interrupt-cells = <2>; > gpio-ranges = <&tlmm 0 0 157>; > > + sdc2_off_state: sdc2-off-state { > + clk-pins { > + pins = "sdc2_clk"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + cmd-pins { > + pins = "sdc2_cmd"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + data-pins { > + pins = "sdc2_data"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + }; > + > + sdc2_on_state: sdc2-on-state { > + clk-pins { > + pins = "sdc2_clk"; > + drive-strength = <16>; > + bias-disable; > + }; > + > + cmd-pins { > + pins = "sdc2_cmd"; > + drive-strength = <10>; > + bias-pull-up; > + }; > + > + data-pins { > + pins = "sdc2_data"; > + drive-strength = <10>; > + bias-pull-up; > + }; > + }; > + > qup_uart9_default: qup-uart9-default-state { > pins = "gpio25", "gpio26"; > function = "qup13_f2";