Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Message-ID: <ae0fd778eb31416eedb248e2cd4faef576174937.camel@pengutronix.de>
Subject: Re: [PATCH v1] soc: imx: imx8mp-blk-ctrl: Add PCIe SYSPLL
 configurations
From:   Lucas Stach <l.stach@pengutronix.de>
To:     Shawn Guo <shawnguo@kernel.org>, Richard Zhu <hongxing.zhu@nxp.com>
Cc:     marex@denx.de, tharvey@gateworks.com, vkoul@kernel.org,
        bhelgaas@google.com, lorenzo.pieralisi@arm.com,
        alexander.stein@ew.tq-group.com, richard.leitner@linux.dev,
        devicetree@vger.kernel.org, linux-pci@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,
        kernel@pengutronix.de, linux-imx@nxp.com
Date:   Tue, 01 Nov 2022 09:44:41 +0100
In-Reply-To: <20221029084514.GT125525@dragon>
References: <1666590189-1364-1-git-send-email-hongxing.zhu@nxp.com>
         <20221029084514.GT125525@dragon>
Content-Type: text/plain; charset="UTF-8"
User-Agent: Evolution 3.40.4 (3.40.4-1.fc34) 
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Precedence: bulk

Hi Shawn, Richard,

Am Samstag, dem 29.10.2022 um 16:45 +0800 schrieb Shawn Guo:
> On Mon, Oct 24, 2022 at 01:43:09PM +0800, Richard Zhu wrote:
> > Add PCIe SYSPLL configurations, thus the internal SYSPLL can be used as
> > i.MX8MP PCIe reference clock.
> > 
> > The following properties of PHY dts node should be changed accordingly.
> >   - Set 'fsl,refclk-pad-mode' as '<IMX8_PCIE_REFCLK_PAD_OUTPUT>'.
> >   - Change 'clocks' to '<&clk IMX8MP_CLK_HSIO_ROOT>'.
> > 
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> 
> Applied, thanks!

Sorry for the late reply, but I'm not really happy with the fact that
the PLL is now unconditionally enabled, even though it is only needed
when there is no external reference clock source.
I fear that this will be hard to correct later on as the DT abstraction
is wrong, as IMX8MP_CLK_HSIO_ROOT is NOT the reference clock for the
PHY, but the PLL generated clock, which isn't properly exposed with
this series.

I'm not happy to see this going in in the current state and if not too
late would like to ask Shawn to remove it from the tree again.

Regards,
Lucas