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From:   <Tharunkumar.Pasumarthi@microchip.com>
To:     <ilpo.jarvinen@linux.intel.com>,
        <Kumaravel.Thiagarajan@microchip.com>
CC:     <gregkh@linuxfoundation.org>, <jirislaby@kernel.org>,
        <andy.shevchenko@gmail.com>, <u.kleine-koenig@pengutronix.de>,
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        <UNGLinuxDriver@microchip.com>
Subject: RE: [PATCH v2 tty-next 2/3] 8250: microchip: pci1xxxx: Add rs485
 support to quad-uart driver.
Thread-Topic: [PATCH v2 tty-next 2/3] 8250: microchip: pci1xxxx: Add rs485
 support to quad-uart driver.
Thread-Index: AQHY1V0xlQ9ney05Q0yTvysx01RZiK38Y4YAgC3ztyA=
Date:   Tue, 1 Nov 2022 14:53:25 +0000
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References: <20221001061507.3508603-1-kumaravel.thiagarajan@microchip.com>
 <20221001061507.3508603-3-kumaravel.thiagarajan@microchip.com>
 <e433da81-46d5-5aad-4ce9-6d48b2e674e@linux.intel.com>
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> From: Ilpo J=E4rvinen <ilpo.jarvinen@linux.intel.com>
> Sent: Monday, October 3, 2022 2:34 PM
> To: Kumaravel Thiagarajan - I21417
> <Kumaravel.Thiagarajan@microchip.com>
> Subject: Re: [PATCH v2 tty-next 2/3] 8250: microchip: pci1xxxx: Add rs485
> support to quad-uart driver.
>=20
> [Some people who received this message don't often get email from
> ilpo.jarvinen@linux.intel.com. Learn why this is important at
> https://aka.ms/LearnAboutSenderIdentification ]
>=20
> EXTERNAL EMAIL: Do not click links or open attachments unless you know th=
e
> content is safe
>=20
> > +     if (rs485->flags & SER_RS485_ENABLED) {
> > +             memset(rs485->padding, 0, sizeof(rs485->padding));
>=20
> Core handles this for you.

I went through the code and it seems like this is not taken care by the cor=
e.
Do you suggest calling 'serial8250_em485_config' inside 'pci1xxxx_rs485_con=
fig' callback?
This has not been done since we do not need all the configurations done ins=
ide 'serial8250_em485_config'.

> > +             if (!(rs485->flags & SER_RS485_RTS_ON_SEND)) {
> > +                     data |=3D ADCL_CFG_POL_SEL;
> > +                     rs485->flags |=3D  SER_RS485_RTS_AFTER_SEND;
> > +             } else {
> > +                     rs485->flags &=3D ~SER_RS485_RTS_AFTER_SEND;
> > +             }
>=20
> Core handles that flags sanitization for you.

I went through the code and it seems like this is not taken care by the cor=
e.
Do you suggest calling 'serial8250_em485_config' inside 'pci1xxxx_rs485_con=
fig' callback?
This has not been done since we do not need all the configurations done ins=
ide 'serial8250_em485_config'.

> > +     } else {
> > +             memset(rs485, 0, sizeof(*rs485));
>=20
> Core handles this.

I went through the code and it seems like this is not taken care by the cor=
e.
Do you suggest calling 'serial8250_em485_config' inside 'pci1xxxx_rs485_con=
fig' callback?
This has not been done since we do not need all the configurations done ins=
ide 'serial8250_em485_config'.

> > +     writeb(data, (port->membase + ADCL_CFG_REG));
> > +     port->rs485 =3D *rs485;
>=20
> Core handles this.

I went through the code and it seems like this is not taken care by the cor=
e.
Do you suggest calling 'serial8250_em485_config' inside 'pci1xxxx_rs485_con=
fig' callback?
This has not been done since we do not need all the configurations done ins=
ide 'serial8250_em485_config'.


Thanks,
Tharun Kumar P