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From:   "Huang, Ying" <ying.huang@intel.com>
To:     Michal Hocko <mhocko@suse.com>
Cc:     Bharata B Rao <bharata@amd.com>,
        Aneesh Kumar K V <aneesh.kumar@linux.ibm.com>,
        linux-mm@kvack.org, linux-kernel@vger.kernel.org,
        Andrew Morton <akpm@linux-foundation.org>,
        Alistair Popple <apopple@nvidia.com>,
        Dan Williams <dan.j.williams@intel.com>,
        Dave Hansen <dave.hansen@intel.com>,
        Davidlohr Bueso <dave@stgolabs.net>,
        Hesham Almatary <hesham.almatary@huawei.com>,
        Jagdish Gediya <jvgediya.oss@gmail.com>,
        Johannes Weiner <hannes@cmpxchg.org>,
        Jonathan Cameron <Jonathan.Cameron@huawei.com>,
        Tim Chen <tim.c.chen@intel.com>, Wei Xu <weixugc@google.com>,
        Yang Shi <shy828301@gmail.com>
Subject: Re: [RFC] memory tiering: use small chunk size and more tiers
In-Reply-To: <Y2IhiSnpQsmY7khx@dhcp22.suse.cz> (Michal Hocko's message of
        "Wed, 2 Nov 2022 08:51:37 +0100")
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        <0d938c9f-c810-b10a-e489-c2b312475c52@amd.com>
        <87tu3oibyr.fsf@yhuang6-desk2.ccr.corp.intel.com>
        <07912a0d-eb91-a6ef-2b9d-74593805f29e@amd.com>
        <87leowepz6.fsf@yhuang6-desk2.ccr.corp.intel.com>
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        <Y2IhiSnpQsmY7khx@dhcp22.suse.cz>
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Date:   Wed, 02 Nov 2022 16:02:54 +0800
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Michal Hocko <mhocko@suse.com> writes:

> On Wed 02-11-22 08:39:49, Huang, Ying wrote:
>> Michal Hocko <mhocko@suse.com> writes:
>> 
>> > On Mon 31-10-22 09:33:49, Huang, Ying wrote:
>> > [...]
>> >> In the upstream implementation, 4 tiers are possible below DRAM.  That's
>> >> enough for now.  But in the long run, it may be better to define more.
>> >> 100 possible tiers below DRAM may be too extreme.
>> >
>> > I am just curious. Is any configurations with more than couple of tiers
>> > even manageable? I mean applications have been struggling even with
>> > regular NUMA systems for years and vast majority of them is largerly
>> > NUMA unaware. How are they going to configure for a more complex system
>> > when a) there is no resource access control so whatever you aim for
>> > might not be available and b) in which situations there is going to be a
>> > demand only for subset of tears (GPU memory?) ?
>> 
>> Sorry for confusing.  I think that there are only several (less than 10)
>> tiers in a system in practice.  Yes, here, I suggested to define 100 (10
>> in the later text) POSSIBLE tiers below DRAM.  My intention isn't to
>> manage a system with tens memory tiers.  Instead, my intention is to
>> avoid to put 2 memory types into one memory tier by accident via make
>> the abstract distance range of each memory tier as small as possible.
>> More possible memory tiers, smaller abstract distance range of each
>> memory tier.
>
> TBH I do not really understand how tweaking ranges helps anything.
> IIUC drivers are free to assign any abstract distance so they will clash
> without any higher level coordination.

Yes.  That's possible.  Each memory tier corresponds to one abstract
distance range.  The larger the range is, the higher the possibility of
clashing is.  So I suggest to make the abstract distance range smaller
to reduce the possibility of clashing.

Best Regards,
Huang, Ying