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From:   "Havalige, Thippeswamy" <thippeswamy.havalige@amd.com>
To:     Rob Herring <robh@kernel.org>
CC:     "robh+dt@kernel.org" <robh+dt@kernel.org>,
        "bhelgaas@google.com" <bhelgaas@google.com>,
        "michals@xilinx.com" <michals@xilinx.com>,
        "krzysztof.kozlowski@linaro.org" <krzysztof.kozlowski@linaro.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "Yeleswarapu, Nagaradhesh" <nagaradhesh.yeleswarapu@amd.com>,
        "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
        "Gogada, Bharat Kumar" <bharat.kumar.gogada@amd.com>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>
Subject: RE: [PATCH v2 2/2] dt-bindings: PCI: xilinx-nwl: Convert to YAML
 schemas of Xilinx NWL PCIe Root Port Bridge
Thread-Topic: [PATCH v2 2/2] dt-bindings: PCI: xilinx-nwl: Convert to YAML
 schemas of Xilinx NWL PCIe Root Port Bridge
Thread-Index: AQHY7bHIoNpmBC8xCE6+Irf4+WDxP64p9mYAgAF0uuA=
Date:   Wed, 2 Nov 2022 10:11:56 +0000
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References: <20221101052049.3946283-1-thippeswamy.havalige@amd.com>
 <20221101052049.3946283-2-thippeswamy.havalige@amd.com>
 <166730310310.897892.15492131590720845659.robh@kernel.org>
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Hi Rob,

Accepted the review comments and ll update the patch and send those again.

Regards,
Thippeswamy H
> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: Tuesday, November 1, 2022 5:26 PM
> To: Havalige, Thippeswamy <thippeswamy.havalige@amd.com>
> Cc: robh+dt@kernel.org; bhelgaas@google.com; michals@xilinx.com;
> krzysztof.kozlowski@linaro.org; linux-kernel@vger.kernel.org; Yeleswarapu=
,
> Nagaradhesh <nagaradhesh.yeleswarapu@amd.com>; linux-
> pci@vger.kernel.org; Gogada, Bharat Kumar
> <bharat.kumar.gogada@amd.com>; devicetree@vger.kernel.org
> Subject: Re: [PATCH v2 2/2] dt-bindings: PCI: xilinx-nwl: Convert to YAML
> schemas of Xilinx NWL PCIe Root Port Bridge
>=20
>=20
> On Tue, 01 Nov 2022 10:50:49 +0530, Thippeswamy Havalige wrote:
> > Convert to YAML schemas for Xilinx NWL PCIe Root Port Bridge dt
> > binding.
> >
> > Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
> > ---
> >  .../bindings/pci/xilinx-nwl-pcie.txt          |  73 ----------
> >  .../bindings/pci/xlnx,nwl-pcie.yaml           | 137 ++++++++++++++++++
> >  2 files changed, 137 insertions(+), 73 deletions(-)  delete mode
> > 100644 Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
> >  create mode 100644
> > Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
> >
>=20
> Running 'make dtbs_check' with the schema in this patch gives the followi=
ng
> warnings. Consider if they are expected or the schema is incorrect. These
> may not be new warnings.
>=20
> Note that it is not yet a requirement to have 0 warnings for dtbs_check.
> This will change in the future.
>=20
> Full log is available here: https://patchwork.ozlabs.org/patch/
>=20
>=20
> pcie@fd0e0000: Unevaluated properties are not allowed ('iommus', 'power-
> domains' were unexpected)
> 	arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dtb
> 	arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dtb
> 	arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dtb
> 	arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dtb
> 	arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dtb
> 	arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dtb
> 	arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dtb
> 	arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dtb
> 	arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dtb
> 	arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dtb
> 	arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dtb
> 	arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dtb
> 	arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dtb
> 	arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.1.dtb
> 	arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dtb
> 	arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dtb
> 	arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dtb
> 	arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dtb
> 	arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dtb
> 	arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dtb