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From:   =?UTF-8?q?K=C3=B6ry=20Maincent?= <kory.maincent@bootlin.com>
To:     viresh.kumar@linaro.org,
        Shiraz Hashim <shiraz.linux.kernel@gmail.com>,
        Vipin Kumar <vipin.kumar@st.com>,
        Vijay Kumar Mishra <vijay.kumar@st.com>,
        Deepak Sikri <deepak.sikri@st.com>,
        linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Cc:     Kory Maincent <kory.maincent@bootlin.com>,
        thomas.petazzoni@bootlin.com, Viresh Kumar <vireshk@kernel.org>,
        soc@kernel.org, Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Russell King <linux@armlinux.org.uk>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>, Arnd Bergmann <arnd@arndb.de>,
        Sudeep Holla <sudeep.holla@arm.com>,
        Gregory CLEMENT <gregory.clement@bootlin.com>,
        Neil Armstrong <neil.armstrong@linaro.org>,
        Alexandre Ghiti <alexandre.ghiti@canonical.com>,
        Rajeev Kumar <rajeev-dlh.kumar@st.com>,
        Vipul Kumar Samar <vipulkumar.samar@st.com>
Subject: [PATCH v2 0/6] Support new features to the SPEAr600
Date:   Wed,  2 Nov 2022 18:10:04 +0100
Message-Id: <20221102171012.49150-1-kory.maincent@bootlin.com>
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From: Kory Maincent <kory.maincent@bootlin.com>

This patches series adds two features of the SPEAr600 SOC:

- Enable the display controller

- Enable the SPI buses using the SSP controller

Changes in v2:
- Keep the I2C_CONFIG in the spear6xx_defconfig while enabling DRM.
- Send cover letter which was not sent in v1 due to a mistake in my git
  mail config.

Viresh, will you take the patches and submit a pull request to the ARM SoC
maintainers?

Kory Maincent (6):
  arm: configs: spear6xx: Refresh defconfig
  arm: dts: spear600: Fix clcd interrupt
  arm: configs: spear6xx: Enable PL110 display controller
  clk: spear: Fix CLCD clock definition on SPEAr600
  arm: dts: spear600: Add ssp controller nodes
  clk: spear: Fix SSP clock definition on SPEAr600

 arch/arm/boot/dts/spear600.dtsi     | 32 ++++++++++++++++++++++++++++-
 arch/arm/configs/spear6xx_defconfig |  7 ++-----
 drivers/clk/spear/spear6xx_clock.c  |  8 ++++----
 3 files changed, 37 insertions(+), 10 deletions(-)

-- 
2.25.1