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Date:   Thu, 3 Nov 2022 18:27:29 +0800
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Subject: Re: [PATCH V2 13/15] arm64: dts: imx8mm-evk: Enable usdhc1 to support
 wifi
Content-Language: en-US
To:     Marco Felsch <m.felsch@pengutronix.de>
Cc:     robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
        shawnguo@kernel.org, s.hauer@pengutronix.de,
        Sherry Sun <sherry.sun@nxp.com>, devicetree@vger.kernel.org,
        Peng Fan <peng.fan@nxp.com>, linux-kernel@vger.kernel.org,
        linux-imx@nxp.com, kernel@pengutronix.de, festevam@gmail.com,
        linux-arm-kernel@lists.infradead.org
References: <20221024031351.4135651-1-peng.fan@oss.nxp.com>
 <20221024031351.4135651-14-peng.fan@oss.nxp.com>
 <20221028144224.dthligupldj2wift@pengutronix.de>
From:   Peng Fan <peng.fan@oss.nxp.com>
In-Reply-To: <20221028144224.dthligupldj2wift@pengutronix.de>
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On 10/28/2022 10:42 PM, Marco Felsch wrote:
> On 22-10-24, Peng Fan (OSS) wrote:
>> From: Sherry Sun <sherry.sun@nxp.com>
>>
>> Enable usdhc1 which is used for wifi.
>>
>> Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
>> Signed-off-by: Peng Fan <peng.fan@nxp.com>
>> ---
>>   arch/arm64/boot/dts/freescale/imx8mm-evk.dts  | 23 +++++++++++
>>   arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 39 +++++++++++++++++++
>>   2 files changed, 62 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
>> index a2b24d4d4e3e..c93387fcd498 100644
>> --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
>> +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
>> @@ -15,6 +15,17 @@ / {
>>   	aliases {
>>   		spi0 = &flexspi;
>>   	};
>> +
>> +	reg_sd1_vmmc: sd1_regulator {
>> +		compatible = "regulator-fixed";
>> +		regulator-name = "WLAN_EN";
>> +		regulator-min-microvolt = <3300000>;
>> +		regulator-max-microvolt = <3300000>;
>> +		gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>;
>> +		off-on-delay = <20000>;
> 
> This is wrong and also unnecessary for wifi?

Patch 14 fixed this. Directly cherry-pick downstream
patch cause this, I will fix.

Thanks,
Peng.

> 
> Regards,
>    Marco
> 
>> +		startup-delay-us = <100>;
>> +		enable-active-high;
>> +	};
>>   };
>>   
>>   &ddrc {
>> @@ -53,6 +64,18 @@ flash@0 {
>>   	};
>>   };
>>   
>> +&usdhc1 {
>> +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
>> +	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
>> +	pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
>> +	pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
>> +	bus-width = <4>;
>> +	vmmc-supply = <&reg_sd1_vmmc>;
>> +	keep-power-in-suspend;
>> +	non-removable;
>> +	status = "okay";
>> +};
>> +
>>   &usdhc3 {
>>   	assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
>>   	assigned-clock-rates = <400000000>;
>> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
>> index 7d6317d95b13..ce450965e837 100644
>> --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
>> +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
>> @@ -559,6 +559,45 @@ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
>>   		>;
>>   	};
>>   
>> +	pinctrl_usdhc1_gpio: usdhc1grpgpio {
>> +		fsl,pins = <
>> +			MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10	0x41
>> +		>;
>> +	};
>> +
>> +	pinctrl_usdhc1: usdhc1grp {
>> +		fsl,pins = <
>> +			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190
>> +			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0
>> +			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
>> +			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
>> +			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
>> +			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
>> +		>;
>> +	};
>> +
>> +	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
>> +		fsl,pins = <
>> +			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x194
>> +			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4
>> +			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4
>> +			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4
>> +			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4
>> +			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4
>> +		>;
>> +	};
>> +
>> +	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
>> +		fsl,pins = <
>> +			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x196
>> +			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6
>> +			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6
>> +			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6
>> +			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6
>> +			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6
>> +		>;
>> +	};
>> +
>>   	pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
>>   		fsl,pins = <
>>   			MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15	0x1c4
>> -- 
>> 2.37.1
>>
>>
>>